CAREER: A Compiler-Assisted Approach to High Performance Memory Architectures

处理器速度和存储器延迟之间的日益扩大的差距将继续成为计算机系统性能的关键问题。 延迟问题在共享相同空间的多处理器上甚至更加严重，其中主存储器模块通常远离所有处理器或除了一个之外的所有处理器。 因此，重要的是减少不必要的远程内存引用和不必要的网络活动，并在私有主缓存中实现高命中率。 该项目探索了编译器和内存架构的一致设计，以改善平均内存延迟和网络流量。 这项工作的主旨是将联合收割机编译器预测程序行为的能力与硬件在运行时记录内存引用模式的能力结合起来。 研究主要集中在三个方面：（1）在具有私有缓存的多处理器上使用编译器辅助和硬件控制的一致性机制：（2）通过数组数据流分析和静态任务调度，使用复杂的过程间分析来支持所提出的一致性机制;（3）程序转换、虚假共享和有限目录指针对所提出的一致性机制的影响。 这项工作涵盖了各种多处理器，共享一个共同的地址空间，包括基于总线的系统，非均匀访问（NUMA）的多处理器和高速缓存存储器访问（COMA）的多处理器。 PI在此资助期内的教育计划的主要目标是：（1）重新设计明尼苏达州计算机科学系的编译器和语言设计课程序列，并巩固这些资源与其他语言设计资源的接口;（二）通过研讨会课程增加主要的编译器和语言设计资源，这些课程解决了有关编译器与其他语言接口的新问题（3）在这些课程中实现卓越的教学，以便使学生能够牢固地理解程序设计语言的设计和实现原理以及编译器技术，这对他们的科学和工程生涯至关重要。 PI将在本资助期内进行两项实验。一个是开发在编译器课程之后教授的语言设计源代码，另一个是在课程中添加操作系统实现课程。 PI的其他教育活动包括探索新的途径，为计算机系统领域的学生创建行业合作计划，并探索新的途径或为专业人士提供良好的基础课程和研讨会课程，例如通过大学的分布式多媒体学习中心。

The widening gap between processor speed and memory latency will continue to be a critical issue to the performance of computer systems. The latency problem is even more acute on multiprocessors that share the same space, in which a main memory module is typically remote to all or all but one of the processors. It is therefore important to reduce unnecessary remote memory references and unnecessary network activities, and to achieve high hit ratio at the private, primary caches. The project explores coherent designs of compilers and memory architectures to improve the average memory latency, and the network traffic. The main thrust of this work is to combine compilers' ability to predict program behavior with harrdware's ability to record memory reference patterns at run time. The research focuses on three major issues: (1) The use of a compiler-assisted and hardware controlled coherence mechanism on multiprocessors with private cache memories; (2) The use of sophisticated interprocedural analysis to support the proposed coherence mechanism, via array data flow analysis and static task scheduling; and (3) The effects of program transformations, false sharing and limited directory pointers on the proposed coherence mechanism. This work covers a variety of multiprocessors that share a common address space, including bus-based systems, the Non-Uniform Access (NUMA) multiprocessors and the Cache-Only Memory Access (COMA) multiprocessors. The main objectives of the PI's education plan in this funding period are (1) to redesign the compiler and language design course sequence for the Computer Science Department of Minnesota and to solidify the interfaces of these sources with other language design sources; (2) to augment the main compiler and language design sources by seminar courses which address new issues regarding the interfaces of the compilers with the rest of the computer systems, and (3) to achieve teaching excellence in these c ourses so as to provide students solid understanding of the principles of programming language design and implementation and compiler techniques which will be important to their scientific and engineering career. The PI will conduct two experiments in this funding period. One is to develop a language design source to be taught after the compiler courses and the other is to add an operating system implementation course to the curriculum. Additional educational activities of the PI include exploration of new avenues for creating industry co-op programs for students in the computer systems area and exploration of new avenues or providing professionals with excellent access to both the basic courses and the seminar courses, e.g. through the university's Distributed Multimedia Learning Center.