Advances in Register Allocation and Efficient Run-Time Program Analysis

该项目涉及现代计算机体系结构的寄存器优化技术。在现代流水线架构中，代码被仔细调度以避免不必要的延迟。然而，一些延迟时隙可能是不可避免的。该项目将开发技术来收集未填满的延迟时隙，以执行通常被认为不值得的工作，例如将有效范围划分为较短的范围。较短的范围会导致较少的寄存器冲突，从而允许将寄存器用于其他目的。通常情况下，不跨过程边界使用寄存器。该项目将开发在程序间一级以最佳方式分配寄存器的技术。更具体地说，这些技术将试图避免调用方/被调用方边界上不必要的寄存器溢出。该项目还将调查使用空闲处理器执行各种程序正确性分析的情况。这是通过一个仅在处理器空闲时执行的“影子”进程来实现的。

This project deals with register optimization techniques for modern computer architectures. In modern pipelined architectures code is carefully scheduled to avoid unnecessary delays. However, some delay slots may be unavoidable. This project will develop techniques to `glean` unfilled delay slots to perform work normally considered not worthwhile, such as splitting live ranges into shorter ranges. Shorter ranges induce fewer register conflicts, allowing registers to be used for other purposes. Normally,registers are not used across procedure boundaries. The project will develop techniques to optimally allocate registers at the interprocedural level. More specifically, the techniques will attempt to avoid unnecessary register spilling on caller/callee boundaries. The project will also investigate the use of idle processors to perform a variety of program correctness analyses. This is achieved using a `shadow` process which executes only when a processor becomes idle.