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Development of an Undergraduate VLSI Test Laboratory for Digital, Analog and Mixed-Signal Circuits

Development of an Undergraduate VLSI Test Laboratory for Digital, Analog and Mixed-Signal Circuits
数字、模拟和混合信号电路本科 VLSI 测试实验室的开发
批准号:
9650672
负责人:
Ramalingam Sridhar
金额:
$3.9万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1996
资助国家:
美国
项目状态:
已结题
起止时间:
1996-07-01 至 1999-06-30

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中文摘要
翻译
这个项目的目的是开发一个用于测试数字、模拟和混合信号电路的本科生VLSI实验室。该实验室包括一个基于CMT混合信号测试台和高速示波器的综合测试平台。该实验室旨在补充现有的两门本科课程:VLSI电子学导论和VLSI测试,并为本科生提供急需的实践经验。这一过程将使本科生能够学习混合信号VLSI电路设计,从初始规范到实际实施。电信、高性能计算和汽车电子领域对混合信号技术的需求激增,因此有必要在本科生水平上引入这项技术。在自动化设计和测试工具的帮助下,快速原型制作被认为是为学生提供典型VLSI系统设计、调试和评估中各个步骤的清晰概念的最合适方法。充分利用新的实验室,开设一门新的课程,重点是VLSI中模拟和混合信号电路的高级设计问题。现有课程的升级在本科课程的VLSI轨道上提供了教唆推荐的有意义的专业设计经验(MMDE)。这一新实验室预计将对大约三分之二的欧洲经委会本科生产生直接影响。该项目的实践经验可以增加学生在领先行业的就业机会,这些技能在这些行业非常有价值。
英文摘要
The purpose of this project is the development of an undergraduate VLSI laboratory for testing digital, analog, and mixed-signal circuits. The lab includes an integrated test platform based on a CMT Mixed-Signal Test Station and a high-speed oscilloscope. The laboratory is intended to supplement two existing undergraduate courses, Introduction to VLSI Electronics and VLSI Testing, and to provide much needed hands-on experience for the undergraduate students. This process will enable the undergraduate students to take a mixed-signal VLSI circuit design from initial specifications to a working implementation. The skyrocketing demands for mixed-signal technology in telecommunication, high-performance computing, and automotive electronics have necessitated the introduction of this technology at the undergraduate level. Rapid prototyping with the help of automated design and test tools is perceived as the most appropriate method of providing the students with a clear concept of the various steps in the design, debugging, and evaluation of a typical VLSI system. A new course focusing on the advanced design issues of analog and mixed-signal circuits in VLSI is to be offered, fully utilizing the new laboratory. The upgrading of the existing courses provides the ABET-recommended major meaningful design experience (MMDE) in the VLSI track of the undergraduate curriculum. This new laboratory is expected to have a direct impact on about two-thirds of the undergraduate ECE students. The project's practical experiences can enhance the job opportunities for the students in leading industries, where such skills are of great value.
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RIA: High-Performance VLSI Systems Using CMOS Wave- Pipelined Transmission Gate Logic
  • 批准号:
    9409762
  • 项目类别:
    Standard Grant
  • 资助金额:
    $9.74万
  • 财政年份:
    1994
  • 负责人:
    Ramalingam Sridhar
  • 依托单位:
海外基金