Design Automation of System-Level Interconnect

电子设计的趋势是朝着更小、更强大的电子系统组成的许多超大规模集成电路芯片，他们的设计需要新的自动化能力。本研究的具体问题是建模和综合电子系统级互连，并开发算法和技术，将适用于更广泛的系统的设计自动化。该方法是开发一种通用的，但近似的，适合于前端设计的大型系统级互连的电感耦合建模能力。例如，电感耦合作为互连尺寸和间距的函数的表示正在确定，以便可以获得性能与成本的权衡分析。在控制响应阻尼、耦合噪声和延迟的基础上，探讨了互连设计优良性的度量方法。此外，正在寻求一种解决耦合线的复杂问题的一般方法，并包括开发提取能力的手段。这项工作的结果也将考虑设计自动化更一般的问题，如机电系统的设计。

The trend in electronic design is toward smaller, more powerful electronic systems composed of many VLSI chips, and their design requires new automation capabilities. This research is on the specific problem of modeling and synthesizing electronic system level interconnect, and developing algorithms and techniques that will be applicable to design automation of even broader systems. The approach is to develop a general, but approximate, capability for modeling inductive coupling of large scale system-level interconnect that is suitable for front-end design. For example, the representation of inductance coupling as a function of interconnect dimensions and spacing is being determined so that performance vs. cost trade-off analysis can be obtained. Measures of interconnect design goodness based on controlling the response damping, coupling noise, and delay are being explored. Moreover, a general approach, which addresses the complex problem of coupled lines, and includes a means of exploiting extraction capabilities is being pursued. The results of this work will also be considered for design automation of more general problems, such as electro-mechanical system design.