Techniques and Tools for Estimating and Improving the Yield and Reliability of VLSI Circuits

半导体制造技术现在可以在一个芯片上放置多达5000万个器件，并允许时钟速度接近GHz范围。 然而，这些进步伴随着更大的产量损失（灾难性的和参数性的）和更低的可靠性。该项目是关于改进产量可靠性估计和提高的技术开发。这些技术包括分层成品率估计和提高，最小扰动方法的成品率和可靠性的提高和新的方法，串扰和电迁移最小化。在成品率，可靠性和其他优化目标，如速度和面积之间的权衡，以及正在调查。这项研究强调集成的产量和可靠性提高的目标与性能和面积的主要目标，同时保持设计数据量可管理。该项目的一个主要重点是通过实施新技术并将其集成到现有的设计框架中来证明新技术的优势。

Semiconductor manufacturing technologies now enable the placement of up to 50 million devices on one die, and allow clock speeds to approach the GHz range. These advances, however, are accompanied by larger yield losses (both catastrophic and parametric) and lower reliability. This project is on the development of techniques for improved yield-reliability estimation and enhancement. These techniques include hierarchical yield estimation and enhancement, minimum perturbation approach for yield and reliability enhancement and new methods for crosstalk and electromigration minimization. The tradeoffs among yield, reliability and other optimization goals such as speed and area, are being investigated as well. This research emphasizes the integration of the yield and reliability enhancement objectives with the primary goals of performance and area, while keeping design data volumes manageable. A major focus of the project is on proving the advantages of the new techniques by implementing and integrating them into existing design frameworks.