SBIR Phase II: Boundary Scan and Built-In Self Test (BIST) Insertion into VHDL Designs with Commercial Off-the-Shelf (COTS) Components or Embedded Cores

* 9801308 Stoel 这个小型企业创新研究第11阶段项目提供了一个解决方案，以应对商业现货（COTS）组件对可测试性的负面影响。 在电子行业中，上市时间不断缩短，因此对COTS组件的需求不断增加，以缩短开发时间。 在使用知识产权（IP）核的芯片级，主要问题是嵌入式核的主要输入的可控性和主要输出的可观测性。 ASC开发了一种基于边界扫描标准的解决方案，该标准适用于所有内核。 为了避免高电路开销和长测试时间，ASC在第一阶段开发了一种优化方法，该方法提供：直接访问每个嵌入式内核，测试时间短，硬件开销低，测试配置灵活。 在第二阶段，ASC将增强其现有的VBIT（R）工具，使设计人员能够自动插入优化的边界扫描在他们的芯片设计与嵌入式核心。 这个新的VBIT-MC（多核）工具将集成到现有的EDA设计流程中，能够使用现有的测试数据，并具有图形化前端。 随着测试工具市场的快速增长，并且没有竞争对手，VBIT-MC的商业前景非常好。 ***

*** 9801308 Stoel This Small Business Innovation Research Phase 11 project provides a solution to deal with the negative impact that commercial off-the-shelf (COTS) components have on testability. The ever shrinking time-to-market, in the electronics industry, has created an increasing need for COTS components to slash development time. At the chip level, where Intellectual Property (IP) cores are being used, the main problem is controllability of the primary inputs and observability of the primary outputs of the embedded cores. ASC has developed a solution based on the boundary scan standard being applied to all cores. To avoid high circuitry overhead and long test times, ASC developed an optimization methodology during Phase I, which provides: Direct access to each embedded core, short test times, low hardware overhead, and flexibility in test configuration. During Phase II, ASC will enhance its existing VBIT(R) tool to allow designers to automatically insert optimized boundary scan in their chip designs with embedded cores. This new VBIT-MC (Multi-Core) tool will be integrated into existing EDA design flows, be capable of using existing test data, and have a graphical front-end. With a rapidly growing market for test tools and without competitors on the horizon, the commercial prospects for VBIT-MC are excellent. ***