Prototype and Distribution of Re-programmable Queuing Modules for Scalable Input Buffered Switches

互联网规模的不断扩大和需要服务质量的新应用的出现，使网络交换机缓冲数据的方式发生了根本性的变化。这种对带宽不断增长的需求已将现有输出缓冲和共享缓冲交换机的架构推向最大可扩展性极限。输入缓冲架构通过将排队操作均匀分布在交换机的所有端口来克服可伸缩性限制。然而，扩展交换机的总带宽并不一定能保证单个应用程序的流量得到公平的服务。提供按流排队的交换机公平地分配带宽并提供有限的延迟。现有的交换机要么提供可扩展性，要么提供按流排队，但没有一台同时提供这两种功能。本研究将实现一个新的硬件模块，使可扩展交换机能够提供按流排队。这个名为WU-IIQ的新模块将为高度可扩展的华盛顿大学千兆位交换机(WUGS)添加增强的排队功能。该卡的逻辑将由现场可编程门阵列(现场可编程门阵列)设备实现，使其能够实现各种排队算法。WU-IIQ将包含用于缓冲ATM信元的大容量同步动态随机存取存储器(SDRAM)和用于存储数据结构和执行按流排队的算法的指针的静态随机存取存储器(SRAM)。WU-IIQ的灵活性使该卡在本机构和其他学术机构的多个应用中备受关注。WU-IIQ上的可重编程逻辑使其能够实现各种按流功能，包括分组调度、流量整形和拥塞控制。虽然所有这些项目都不同，但它们都可以使用相同的硬件来实现。该项目建议实现WU-IIQ硬件，并将其分发给需要这种硬件的研究机构，以试验按流排队机制。该WU-IIQ模块的文件将通过万维网提供。将提供常用硬件函数库，包括实现按流排队操作的函数库。

The growing size of the Internet and the emergence of new applications that require Quality of Servicemandate radical changes in the way that network switches buffer data. This growing demand for bandwidth has pushed the architectures of existing output-buffered and shared-buffer switches to their maximum scalability limits. Input-buffered architectures overcome scalability limits by evenly distributing the queuing operations over all ports of the switch. Scaling the aggregate bandwidth of a switch, however, doesnot necessarily guarantee that an individual application's traffic flow is serviced fairly. Switches that provide per-flow queuing fairly allocate bandwidth and provide bounded delay. Existing switches provide either scalability or per-flow queuing, but none provide both.This research will implement a new hardware module that enables a scalable switch to provide per-flow queuing. This new module, called the WU-iiQ, will add enhanced queuing features to the highly scalable Washington University Gigabit Switch (WUGS). The logic for this card will be implemented with a Field Programmable Gate Array (FPGA) device, enabling it to implement a variety of queuing algorithms. The WU-iiQ will contain high-capacity Synchronous Dynamic Random Access Memory (SDRAM) to buffer ATM cells and Static Random Access Memory (SRAM) to store data structures and pointers for algorithms that perform per-flow queuing.The flexibility of the WU-iiQ has made the card of interest for several applications at this and other academic institutions. The reprogrammable logic on the WU-iiQ enables it to implement a variety of per-flow functions, including packet scheduling, traffic shaping, and congestion control. While all of these projects are different, they can all be implemented by using the same hardware.This project proposes to implement the WU-iiQ hardware and distribute it to research institutions that require such hardware to experiment with per-flow queuing mechanisms. Documentation for this WU-iiQ module will be made available via the World Wide Web. A library of commonly-needed hardware functions, including those that implement per-flow queuing operations, will be available for download.