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SBIR Phase I: Integration and Distribution of Low-Jitter On-Chip Clock for High-Speed Analog-to-Digital Converters

SBIR Phase I: Integration and Distribution of Low-Jitter On-Chip Clock for High-Speed Analog-to-Digital Converters
SBIR 第一阶段:高速模数转换器低抖动片上时钟的集成和分配
批准号:
9861554
负责人:
Deepnarayan Gupta
金额:
$10.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1999
资助国家:
美国
项目状态:
已结题
起止时间:
1999-01-01 至 1999-06-30

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中文摘要
翻译
9861554这个小型企业创新研究第一阶段项目建议集成两种超导技术--快速单磁通量子(RSFQ)和长约瑟夫森结(LJJ)--以构建具有片上时钟的快速数字化仪器。HYPRES已经演示了使用外部时钟的闪存模数转换器(ADC)在16G样本/S下的瞬时脉冲捕获。通过将外部高速时钟替换为具有极低时序抖动的片内时钟,可以增强ADC的性能。片上时钟还通过消除对外部高速时钟源的要求简化了数字化系统。利用欠阻尼长约瑟夫森结的共振孤子模,可以产生具有极窄线宽的高速、频率可调、单通量量子(SFQ)时钟。在第一阶段,将长结主时钟与新的时钟选择电路相结合,并与宽带ADC集成,开发出一种多功能多频时钟发生器。将研究两种时钟分配方案--通过约瑟夫森传输线(JTL)和匹配的低阻抗微带线上的弹道传输。长结片上时钟与闪存ADC的成功集成将导致在第二阶段展示一种更简单、成本更低的瞬时数字化仪器。尽管惯性约束聚变和高能物理等领域的需求不断增长,但能够超过10G样本/S的瞬时数字化仪器目前还没有商业化。HYPRES正在开发这样一种仪器,专注于每年6.3亿美元的数字化仪器市场。取消昂贵的多GHz外部时钟发生器将简化数字化系统并降低其成本。使用宽带ADC的一个副产品商业应用是通信信号处理器,例如数字波束形成,目标是每年5亿美元的卫星通信硬件市场。
英文摘要
9861554 This Small Business Innovation Research Phase I Project proposes to integrate two superconducting technologies--rapid-single-flux-quantum (RSFQ) and long-Josephson-junction (LJJ) - to build a fast digitizer instrument with on-chip clocking. HYPRES has demonstrated transient pulse capture at 16 GSamples/s with a flash analog-to-digital-converter (ADC) using an external clock. The ADC performance can be enhanced by replacing the external high-speed clock with an on-chip clock with very low timing jitter. The on-chip clock also simplifies the digitizer system by removing the requirement of external high-speed clock sources. A high-speed, frequency-tunable, single-flux-quantum (SFQ) clock with extremely narrow line width can be generated utilizing the resonant soliton modes of an underdamped long Josephson junction. In Phase I, a versatile multiple-frequency clock generator will be developed by combining the master long-junction clock with a new clock selector circuit and integrated with the wideband ADC. Two clock distribution schemes - through Josephson transmission lines (JTL) and ballistic transport on matched low-impedance micro-strip lines will be investigated. Successful integration of the long-junction on-chip clock with the flash ADC will lead to the demonstration of a simpler and lower cost transient digitizer instrument in Phase II. A transient digitizer instrument capable of sampling rates above 10 GSamples/s is not commercially available today, in spite of a growing demand in fields such as inertial confinement fusion and high-energy physics. HYPRES is developing such an instrument focusing on the $630M/year market for digitizer instruments. Elimination of expensive multi-GHz external clock generators will simplify the digitizer system and reduce its cost. A spin-off commercial application, employing the wideband ADC, is a communication signal processor, such as digital beam forming, targeted towards the satellite-communication hardware market of $500M/year.
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  • 批准号:
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  • 项目类别:
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  • 资助金额:
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