Lifetime Validation of IP-Based Systems-on-a-Chip

片上系统（soc）包含预先设计的子系统，这些子系统包含来自许多来源的知识产权（IP）。基于IP的设计技术允许使用预先设计的子系统，这有助于设计复杂的关键系统。然而，它在验证中引入了一些基本问题。这项研究正在探索生命周期验证的方法，以确保基于IP的SOC在其预计生命周期内在可接受的正确性范围内运行。在这里，验证意味着确保系统不包含可能导致严重系统故障的未检测到的设计错误或物理故障的任务。一种集成的方法来设计验证和物理故障测试的soc采用组件，其实现或验证状态是不完全已知的。研究主要集中在两个相关问题上：(1)建立设计误差综合模型，从而建立高质量的设计验证方法；(2)验证包含ip式电路的设计。提供独立于实现的故障覆盖的功能测试方法正在开发中。研究包括理论研究和实验工作，使用大学-工业设计，重点是难以检测的故障和安全关键应用。

Systems-on-a-chip (SOCs) contain predesigned subsystems that contain intellectual property (IP) from many sources. IP- based design technologies allow the use of predesigned subsystems, which facilitate the design of complex, critical systems. However, it introduces some fundamental problems in validation. This research is exploring methodologies for lifetime validation for ensuring that an IP based SOC operates within acceptable correctness bounds over its projected lifetime. Here, validation means the task of ensuring that a system contains no undetected design errors or physical faults that can cause a critical system failure. An integrated approach to design verification and physical fault testing for SOCs employing components, whose implementation or validation status is incompletely, known is being pursued. The research focuses on two related issues: (1) devising synthetic models of design errors that lead to high quality design validation methods; and (2) validating designs that contain IP-style circuits. Functional testing methods that provide implementation- independent fault coverage are being developed. The research includes theoretical studies and experimental work using university-industry designs, with emphasis on hard-to-detect faults and safety-critical applications.