Power Analysis and Optimization Methodologies for Wireless Embedded Nanochips

这项研究开发了先进的方法和工具，使未来无线家电的低能耗嵌入式纳米系统芯片的设计成为可能。开发了一种系统级功耗分析技术，该技术考虑了无线协议、架构选择和纳米技术对无线嵌入式纳米芯片的硬件、软件和射频组件的能耗的影响。由于自适应片上通信是这种基于异质组件的纳米芯片的基础，因此针对低能耗的片上通信体系结构和协议开发了分析和优化技术。为了延长移动系统的电池寿命，开发了静态和自适应分析和管理技术。这些技术正被应用于设计一种正在开发的自适应单芯片无线电，以实现无线多媒体通信。

This research develops advanced methodologies and tools to enable the design of low-energy embedded system-on-nanochips for future wireless appliances. A system-level power analysis technique is developed which considers the effects of wireless protocols, architectural choices, and nanometer technologies on the energy consumption of the hardware, software, and RF components of a wireless embedded nanochip. Since adaptive on-chip communication is fundamental to such heterogeneous component-based nanochips, analysis and optimization techniques are developed for low-energy on-chip communication architectures and protocols. Static and adaptive analysis and management techniques are developed to extend the battery life of the mobile systems. The techniques are being applied to the design of an adaptive single-chip radio that is being developed to enable wireless multimedia communications.