SBIR Phase I: Integrated Reactor Scale and Topography Feature Scale Simulator for Plasma Enhanced Semiconductor Processes

这个小型企业创新研究第一阶段项目将开发一个统计(蒙特卡洛)软件模型和软件模拟工具，用于集成电路制造中使用的低压等离子体的预鞘和鞘区域。其目的是在反应堆结垢现象和特征结垢现象之间架起时间/长度尺度的桥梁。护套模型将与现有的反应堆规模软件模型(CFD-ACE+)和功能规模软件模拟器(Speedie和CATS)集成。这项工作将填补等离子体设备和工艺设计师目前面临的空白。它将评估宏观反应堆条件对特征尺度剖面演变的影响。斯坦福大学集成电路中心将是该项目的分包商。第一阶段的工作将集中在基于带电粒子在晶片表面附近传输的动力学处理的中等尺度模型上。该模型将是CFD-ACE+中的流体动力学模型与Speedie和CATS中用于结构间颗粒传输的无碰撞气相模型之间的接口。等离子体预健康模型将为Speedie和CATS提供离子通量、能量和角分布的空间分辨分布。Speedie和CATS都需要芯片级模型，以解决电路布局/地形对物种产生/损失、带电粒子收集和到衬底的电流路径的影响。在第二阶段，这些模型将针对Cl2和SF6系统中的硅蚀刻工艺进行改进和验证(对照斯坦福大学进行的实验)。CATS将扩大到包括晶片充电电路，并将与Speedie合并。该能力的商业可用性将使工艺工程师能够设计更好的工艺，并在物理原型制作之前确定设备/工艺缺陷。该模型的使用将能够减少由于不满意的间隙/台阶覆盖、薄膜不均匀和不期望的刻蚀轮廓而造成的潜在成品率损失。根据行业观察人士的说法，即使制造产量提高2%，也会为该行业带来显著的节省。

This Small Business Innovation Research Phase I project will develop a statistical (Monte Carlo) software model and software simulation tool for the pre-sheath and sheath regions of low pressure plasmas used in IC fabrication. The objective is to bridge the time/length scales between reactor scale phenomena and feature scale phenomena. The sheath models will be integrated with an existing reactor scale software model (CFD-ACE+) and feature scale software simulators (SPEEDIE and CATS). The work will fill a void currently faced by designers of plasma equipment and processes. It will evaluate the influence of macroscopic reactor conditions on feature scale profile evolution. Stanford University Center for Integrated Circuits will be a sub-contractor on this project. The Phase I effort will focus on an intermediate-scale model based on kinetic treatment of charged particle transport near the wafer surface. This model will be an interface between a hydrodynamic model in CFD-ACE+ and collisionless gas phase models in SPEEDIE and CATS for interstructure particle transport. The plasma-presheath model will provide spatially resolved distributions of ion flux, energy and angular distributions to SPEEDIE and CATS. Both SPEEDIE and CATS require die level models to resolve the impact of circuit layout/topography on species generation/loss, charged particle collection and currents paths to the substrate.In Phase II, the models will be refined and validated (against experiments conducted at Stanford) for silicon etch processes in Cl2 and SF6 systems. CATS will be expanded to include the wafer charging circuit and will be merged with SPEEDIE. The commercial availability of the capability will allow process engineers to design better processes and identify equipment/process deficiencies before physical prototyping. The use of the model will enable the reduction of potential yield losses due to unsatisfactory gap/step coverage, film noncomformality and undesirable etch profiles. According to industry observers, even a 2% improvement in the fabrication yield will provide significant savings to the industry.