CAREER: The Long-Term Effects of Technology on Microprocessors

题目：CAREER：技术对微处理器的长期影响（作者：Doug Burger，得克萨斯大学奥斯汀分校）这项由CAREER基金资助的研究旨在解决深亚微米技术带来的微处理器设计挑战中的三个问题：性能增长放缓、可靠性降低和功耗增加。本研究通过在三个设计类别中提出新的技术敏感设计来应对这些挑战：单个微架构核心、大型片上存储系统和片上多处理器。微体系结构研究分为两部分：基于技术的当前微体系结构可扩展性分析，以确定和量化未来的微体系结构瓶颈，以及对网格指令处理器的评估——一种新的微体系结构，包含功能单元的二维阵列，消除了许多微体系结构瓶颈，这些瓶颈将由先进的技术产生。该研究还评估了在未来以电线为主的环境中，如何设计多兆字节的片上存储系统。物理设计（将有成千上万的子库）和逻辑组织（如何将数据映射到具有非均匀的、位置相关延迟的缓存中）都在探索中。最后，资助的研究正在探索通过向每个芯片添加多个处理器/内存块的新机制来加速单线程性能的方法。这些机制包括细粒度计算迁移、动态线程并行化、冗余计算以及基于工作集大小的片上内存动态分配和调整。

ABSTRACTProposal: 9985109Title: CAREER: The Long-Term Effects of Technology on MicroprocessorsPI: Doug Burger, University of Texas at AustinThe research funded by this CAREER grant is addressing three of the microprocessor design challenges posed by deep submicron technologies: slowing performance growth, decreasing reliability, and increasing power dissipation. This research is attacking these challenges by proposing new technology-sensitive designs across three design categories: individual microarchitectural cores, large on-chip memory systems, and chip multiprocessors.The microarchitecture research is organized into two parts: a technology-based scalability analysis of current microarchitectures, to determine and quantify future microarchitectural bottlenecks, and an evaluation of the grid instruction processor--a new microarchitecture, containing two-dimensional arrays of functional units, which eliminates many of the microarchitecture bottlenecks that will arise from advancing technologies.The research is also evaluating how multi-megabyte on-chip memory systems should be designed in future wire-dominated environments. Both the physical design (which will have sub-banks numbering in the thousands) and the logical organization (how to map data into caches with non-uniform, position-dependent latencies) are being explored.Finally, the funded research is exploring ways of accelerating single-thread performance by adding new mechanisms to chips with multiple processor/memory tiles each. These mechanisms include fine-grained computation migration, dynamic thread parallelization, redundant computation, and working set size-based dynamic allocation and adjustment of on-chip memory.