Interconnect-Driven CAD Methodologies for VLSI Layout

提出的研究解决了在深亚微米技术中设计互连优化系统的问题。最近对VLSI系统在时序、噪声、功耗和相关问题方面的性能的所有研究都指出互连是一个主要因素。因此，设计低噪声、低功率、高速可靠系统的一个核心挑战是能够估计和优化互连长度、几何形状、位置和延迟，以及通过预测和控制单独导线之间的相互关系来最小化串扰。这些问题通过使用(1)创新的、互连规则的设计表示法(2)分解算法与布局规划以及对互连长度、延迟和串扰的同时预测、估计和优化相结合来解决。还考虑了工艺参数变化的影响。

The proposed research addresses the problem of designing interconnect-optimized systems in deep-sub-micron technologies. All recent studies on the performance of VLSI systems in terms of timing, noise, power dissipation and related problems point to interconnect as a major factor. Thus, a central challenge in designing low-noise, low-power, high-speed reliable systems is to be able to estimate and optimize interconnect lengths, geometrical shapes, locations and thus delays, as well as minimize cross-talk by predicting and controlling mutual relations between individual wires. These problems are addressed by using (1) an innovative, interconnect-regular design representation (2) decomposition algorithms integrated with floorplanning and with simultaneous prediction, estimation and optimization of interconnect lengths, delays and cross-talk. The influence of process parameter variations is also considered.