SBIR Phase I: A Low Cost Semiconductor Metallization-Planarization Process

该小型企业创新研究（SBIR）第一阶段项目将展示半导体规模特征的铜金属化和平面化创新工艺的可行性。 与在整平剂和增亮剂存在下的几何整平或真实整平相比，所提出的电化学沉积工艺基于电荷或法拉第介导的整平。 目前的铜金属化工艺使用难以控制的含有整平剂和光亮剂的电镀浴，并且对于每个处理的8英寸晶片产生30至50升的废浆料。 所提出的电荷调制电化学沉积工艺将在简单、易于控制的电镀浴中操作，并且将消除或基本上减少当前化学/机械加工步骤的浪费和成本。 在第一阶段计划期间，将使用最先进的ULSI晶片建立和验证法拉第介导的整平工艺的理论基础。并提供与半导体工业中现有技术的铜金属化工艺相关的大量成本节约

This Small Business Innovation Research (SBIR) Phase I project will demonstrate the feasibility of an innovative process for copper metallization and planarization of semiconductor scale features. In contrast to geometric leveling or true leveling in the presence of levelers and brighteners, the proposed electrochemical deposition process is based on charge or Faradaic mediated leveling. The current copper metallization process utilizes a difficult to control plating bath containing levelers and brighteners and generates between 30 and 50 liters of waste slurry for each 8-inch wafer processed. The proposed charge modulated electrochemical deposition process will operate in a simple, easily controlled plating bath and will eliminate or substantially reduce the waste and cost of the current chemical/mechanical-processing step. During the Phase I program, the theoretical basis for the Faradaic mediated leveling process will be established and validated using state-of-the-art ULSI wafers.It is anticipated that the Faradaic mediated leveling process will eliminate or substantially reduce (i.e., by greater than 85%) the copper waste slurry and provide substantial cost savings relevant to the state-of-the-art copper metallization processes in the semiconductor industry