ITR: Synthesis of Adaptive Mission-Specific Processors

该项目的目标是开发的设计方法，软件工具和编程环境的自动合成的任务特定的处理器（MSP）的基础上，在加州大学欧文分校开发的Morphosys架构。由于它们的硬件设计不适合应用程序，通用嵌入式处理器架构的面积和功率利用效率低下。另一方面，ASIC不能更新以适应不同的算法改进。通过允许一组目标应用程序来决定体系结构，MSP设计包含了必要的组件和互连，以优化特定程序套件的性能。合成的体系结构是动态可重构的，并支持可重定向编译器，以纳入算法增强或更改任务规范。所提出的方法依赖于编译的程序表示的高级算法语言成数据流图（DFG）格式，并从该格式到VHDL。这项技术是科罗拉多州立大学卡梅隆项目的一部分。一个新的MSP设计框架将被开发，以纳入约束为基础的MSP合成和估计，以及编译支持的合成架构。

The objective of this project is to develop the design methodology, software tools and programming environment for the automated synthesis of Mission-specific Processors (MSPs) based on the Morphosys architecture developed at UC, Irvine. Because their hardware design is not tailored to the application(s), generic embedded processor architectures make inefficient use of area and power. ASICs on the other hand cannot be updated to accommodate different algorithm improvements. By allowing a set of target applications to dictate the architecture, MSP designs incorporate the necessary components and interconnections to optimize the performance of a specific suite of programs. The synthesized architecture is dynamically reconfigurable and supports a retargetable compiler to incorporate algorithm enhancements or changing task specifications. The proposed approach relies on the compilation of a program expressed in a high-level algorithmic language into a data-flow graph (DFG) format and from that format into VHDL. This technology has been developed as part of the Cameron Project at Colorado State University. A new MSP design framework will be developed to incorporate constraint-based MSP synthesis and estimation as well as compilation support for the synthesized architecture.