ITR: High Density Analog Computing Arrays

EIA-0083172哈斯勒，保罗佐治亚理工学院ITR：高密度模拟计算阵列这个项目正在研究一种基于模拟和数字计算的混合实时传感信号处理的替代模型。研究中的阵列直接在改进的EEPROM存储单元中执行模拟计算；每个单元充当乘法器，将输入信号乘以存储在浮动栅极上的模拟值。模拟计算阵列的潜在优势包括比数字计算机更低的延迟、更低的功耗以及对许多模拟输入的并行处理。该项目包括模拟计算阵列的实验演示、模拟和设计工具以使该技术可供DSP设计人员使用，以及对该技术的健壮性和可靠性进行调查。将开发几个单芯片信号处理系统，包括自适应匹配滤波器、倒谱计算器、隐马尔可夫模型系统和多方向滤波器阵列。

EIA-0083172Hasler, PaulGeorgia Institute of TechnologyITR: High Density Analog Computing ArraysThis project is investigating an alternate model of real-time sensory signal processing based upon a mixture of analog and digital computation. The arrays under study perform analog computations directly in modified EEPROM memory cells; each cell acts as a multiplier that multiplies the input signal by an analog value stored on a floating gate. Potential advantages of analog computing arrays include lower latency than digital computers, lower power consumption, and parallel processing of many analog inputs. The project encompasses experimental demonstration of analog computing arrays, simulation and design tools to make the technology accessable to DSP designers, and investigation of the robustness and reliability of the technology. Several single-chip signal processing systems will be developed, including adaptive matched filters, a cepstrum calculater, systems for hidden Markov models, and a multi-directional filter array.