Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC - Three Dimensional Planar Device Integration for Mixed Signal Electronics

这项研究的努力是针对提供一种新的解决方案，与混合信号集成的问题，通过使用平面硅晶体管的三维实现。计划中的研究将探索混合信号技术的可行性，通过研究和开发在不同的单晶器件平面中采用数字和模拟平面晶体管结构的器件和工艺技术，使用低温下的单晶硅层转移技术，并通过将数字和模拟功能隔离在两者之间的接地平面。 这将在继续允许用于信号传输的水平和垂直方向上的大互连密度的同时完成。为了使其可行，已经证明了在低于550 ℃的温度下在平坦化的低粗糙度二氧化硅表面上转移单晶硅的薄（100 nm）层。基于掺杂多晶硅和/或钨的互连和接地平面被结合在单晶硅平面之间。多个平面的使用（其间具有氧化物）还允许并入其他无源元件，同时限制面积的增加以及高频损耗效应的降低。预计这种方法将通过使用接地平面和减少耦合来减少噪声和串扰。 这将为模拟晶体管的设计提供额外的自由度，例如本项目中的金属氧化物半导体场效应晶体管。这种方法也与无源元件的其他发展兼容，并且可以结合无源元件的其他发展，例如高品质因数电感器、滤波器等，在制造过程的后端。这项研究解决了潜在的工业应用的重大问题，因为模拟和数字技术可以在相当大的方式，因为固有的高频或低功耗的设计要求，从彼此不同。维持低成本、低功率操作的需要以及由模拟信号和数字信号之间的干扰引起的电路和系统问题是这些挑战中的一些。

This research effort is directed to providing a novel solution to the problems that occur with mixed-signal integration by using three-dimensional implementation of planar silicon transistors. The planned research will explore mixed signal technology's viability through research and development of device and process technology incorporating digital and analog planar transistor structures in different single-crystal device planes using techniques of single-crystal silicon layer transfer at low temperatures and by isolating the digital and analog functions with a ground-plane in between. This will be done while continuing to allow a large interconnection density in the horizontal and vertical direction for signal transmission. In order to make this feasible, transfer of thin (100's of nm) layers of single-crystal silicon on a planarized low roughness silicon dioxide surface at temperatures below 550 C has been demonstrated. Interconnections and ground planes based on doped poly-silicon and/or tungsten are incorporated in between the single-crystal silicon planes. The use of multiple planes, with oxide in between, also allows incorporation of other passive elements while limiting the increase in area together with a reduction in the loss effects of high frequencies. It is expected that this approach will reduce noise and cross-talk through the use of ground-planes and reduced coupling. This should provide additional freedom in the design of analog transistors, such as the metal-oxide semiconductor field-effect transistors in this project. This approach is also compatible with and can incorporate other developments in passive elements, such as high quality factor inductors, filters, etc., in back-end of the fabrication process. This research addresses significant issues for potential industrial applications , as analog and digital technologies can differ from each other in quite substantial ways because of the design requirements inherent to high frequency or low power. Maintaining low cost, the need for operation at low power, and the circuit and systems issues arising from interference between analog signals and digital signals are a few of these challenges.