Transistor-Based and Voltage-Compatible Nanoscale Memories and Configurable Elements using Phase Transitions

相变导致材料性能的显著变化，并且发生在纳米尺度上。铁电、铁磁、超导等都是可重复发生的相变的例子，并被用于小型化设备。另一种不常用的相变现象是金属-绝缘体相变。铁电和金属绝缘体的转变在使用和制造中与电子器件结构非常兼容。本工作旨在采用一种基于相变现象的新发明来实现具有万亿级密度、纳秒速度和低功耗的10纳米尺度非易失性存储器。这项工作将探索该组件作为独立存储器和可重构性的使用，以有效地实现计算任务。该结构利用单个元件（交叉点晶体管）内浮栅中的相变现象来实现以纳秒速度在1v工作时的滞回特性。这种说法是基于对1000人的探索性论证。S （nm × 1000）S （nm）10nm技术将使集成芯片的密度达到1012位。这些存储元件是通过控制门编程的，可以提供传递功能。这允许一个非常密集的可编程互连结构，其最简单的形式是用单个相变存储器元件取代六晶体管静态随机存取存储器编程元件。这项工作将通过探索缩放、探索作为替代品的新材料、发展对潜在现象的理解以及开发用于使用的模型，将单元素相变存储器的初步演示扩展到纳米尺度。这种存储器本身将成为高密度集成系统非常理想的健壮存储介质。这项工作还将探索这种新元件作为可编程互连元件的使用。这个非常探索性的方向有望通过软件可编程计算取代定制设计，在软件可编程计算中，可以配置和重新配置计算元素之间的高密度互连。这部分工作有可能在功耗和减少定制和昂贵的设计和生产方面提供重大改进。该提案的智力价值在于，它将探索、开发、理解和展示一种纳秒级、低功耗、通用的万亿级存储元件。通过在纳米尺度上实现快速的片上可编程性，这一努力也将为实现可靠的低成本计算指明新的方向。这一努力将产生更广泛的影响，通过(a)开发两堂课的教育课堂材料，可以纳入纳米级器件物理学的顶点课程，(b)包括两名本科生，一名是康奈尔大学的学生，另一名是康奈尔大学以外的学生，在夏季的几个月里，作为本科生研究经历的一部分。在这项工作的第三年，首席研究员还将在一次主要的IEEE会议上组织一次为期一天的高级存储器和架构课程。

Phase transitions result in significant changes in properties of materials and occur down to nanoscale dimensions. Ferroelectric, ferromagnetic, superconductivity, etc. are examples of phase transitions which happen reproducibly and are employed in miniaturized devices. An additional phase transition phenomenon, not as commonly employed, is that of metal-insulator transitions. Ferroelectric and metal-insulator transitions are very compatible with electronic device structures, in use and in fabrication. This work aims to employ a new invention based on phase transition phenomena to achieve 10 nanometer scale non-volatile memory capable of terascale density with nanosecond speeds and low power. The work will explore the use of this component as stand-alone memory and for reconfigurability to efficiently implement computing tasks. The structure employs phase transition phenomena in a floating gate within a single element (a cross-point transistor) to achieve hysteretic characteristics at 1 V of operation at nanosecond speeds. This claim is based on an exploratory demonstration of few 1000?s of nm by 1000?s of nm dimension. The 10 nm capability will lead to 1012 bit density on integrated chips. These memory elements are programmed through control gates and can provide pass functions. This permits a very dense programmable interconnect fabric whose simplest form is the replacement of the six transistor static random access memory programming element by a single phase transition memory element. This effort will extend the preliminary demonstration of the single element phase transition memory to nanoscale by exploring scaling, exploring new materials as replacements, developing the understanding of the underlying phenomena, and developing models for use. Such memories, in themselves, will be a very desirable robust storage medium for highly dense integrated systems. The effort will also explore the use of this new element as a programmable interconnect element. This very exploratory direction holds the promise of replacing custom design, as currently practiced, by software programmable computing where the ability to configure and reconfigure highly dense interconnections between computational elements is utilized. This part of the effort has the potential for providing major improvements in power dissipation and in mitigation of custom and expensive design and production. The intellectual merit of the proposal is that it will explore, develop, understand, and demonstrate a nanosecond low power terascale memory element that will be of universal use. The effort will also point to new directions in achieving reliable low cost computing by implementing fast on-chip programmability at nanoscale. The broader impact of this effort will occur through (a) development of educational class-room material for two lectures that can be incorporated in a capstone course in nanoscale device physics, (b) the inclusion of two undergraduate students, one a student from Cornell during the school year, and the second an under-represented student from outside Cornell during summer months as part of a research experience for undergraduate. The principal investigator will also organize a day-long course on advanced memories and architectures leveraging them at a major IEEE conference in the third year of this effort.