Transistor-Based and Voltage-Compatible Nanoscale Memories and Configurable Elements using Phase Transitions

相变导致材料性质的显著变化，并且发生在纳米尺度下。铁电、铁磁、超导等是相变的实例，其可再现地发生并且用于小型化装置中。另一种不常用的相变现象是金属-绝缘体转变。铁电和金属-绝缘体转变在使用和制造中与电子器件结构非常兼容。这项工作的目的是采用一种新的发明的基础上的相变现象，以实现10纳米规模的非易失性存储器，能够万亿级的密度与纳秒的速度和低功耗。这项工作将探索使用这个组件作为独立的内存和可重构性，以有效地实现计算任务。该结构采用在一个单一的元件（交叉点晶体管）内的浮栅中的相变现象，以实现在纳秒速度下以1 V的操作的滞后特性。这种说法是基于一个探索性的示范几1000？1000 nm？的nm尺寸。10纳米的能力将导致1012位密度的集成芯片。这些存储器元件通过控制栅极被编程并且可以提供通过功能。这允许非常密集的可编程互连结构，其最简单的形式是用单个相变存储器元件代替六晶体管静态随机存取存储器编程元件。这项工作将通过探索缩放，探索新材料作为替代品，发展对潜在现象的理解以及开发使用模型，将单元素相变存储器的初步演示扩展到纳米级。这样的存储器本身将是用于高密度集成系统的非常理想的鲁棒存储介质。这项工作还将探索使用这种新的元素作为一个可编程的互连元件。这个非常探索性的方向有希望通过软件可编程计算来取代目前实践的定制设计，其中利用了配置和重新配置计算元件之间的高密度互连的能力。这部分工作有可能在功耗方面提供重大改进，并减轻定制和昂贵的设计和生产。该提案的智力价值在于，它将探索、开发、理解和展示一种具有普遍用途的纳秒低功耗万亿级存储器元件。这项工作还将指出新的方向，在实现可靠的低成本计算，通过实现快速芯片上的可编程性在纳米级。这一努力的更广泛的影响将通过以下方式发生：（a）为两个讲座开发教育教室材料，这些材料可以纳入纳米器件物理学的顶点课程，（B）纳入两名本科生，一名是康奈尔大学的学生，第二名是康奈尔大学以外的学生，第三名是康奈尔大学夏季的学生，作为本科生研究经验的一部分。首席研究员还将在这项工作的第三年组织一个为期一天的高级存储器和架构课程，在IEEE的一个重要会议上利用它们。

Phase transitions result in significant changes in properties of materials and occur down to nanoscale dimensions. Ferroelectric, ferromagnetic, superconductivity, etc. are examples of phase transitions which happen reproducibly and are employed in miniaturized devices. An additional phase transition phenomenon, not as commonly employed, is that of metal-insulator transitions. Ferroelectric and metal-insulator transitions are very compatible with electronic device structures, in use and in fabrication. This work aims to employ a new invention based on phase transition phenomena to achieve 10 nanometer scale non-volatile memory capable of terascale density with nanosecond speeds and low power. The work will explore the use of this component as stand-alone memory and for reconfigurability to efficiently implement computing tasks. The structure employs phase transition phenomena in a floating gate within a single element (a cross-point transistor) to achieve hysteretic characteristics at 1 V of operation at nanosecond speeds. This claim is based on an exploratory demonstration of few 1000?s of nm by 1000?s of nm dimension. The 10 nm capability will lead to 1012 bit density on integrated chips. These memory elements are programmed through control gates and can provide pass functions. This permits a very dense programmable interconnect fabric whose simplest form is the replacement of the six transistor static random access memory programming element by a single phase transition memory element. This effort will extend the preliminary demonstration of the single element phase transition memory to nanoscale by exploring scaling, exploring new materials as replacements, developing the understanding of the underlying phenomena, and developing models for use. Such memories, in themselves, will be a very desirable robust storage medium for highly dense integrated systems. The effort will also explore the use of this new element as a programmable interconnect element. This very exploratory direction holds the promise of replacing custom design, as currently practiced, by software programmable computing where the ability to configure and reconfigure highly dense interconnections between computational elements is utilized. This part of the effort has the potential for providing major improvements in power dissipation and in mitigation of custom and expensive design and production. The intellectual merit of the proposal is that it will explore, develop, understand, and demonstrate a nanosecond low power terascale memory element that will be of universal use. The effort will also point to new directions in achieving reliable low cost computing by implementing fast on-chip programmability at nanoscale. The broader impact of this effort will occur through (a) development of educational class-room material for two lectures that can be incorporated in a capstone course in nanoscale device physics, (b) the inclusion of two undergraduate students, one a student from Cornell during the school year, and the second an under-represented student from outside Cornell during summer months as part of a research experience for undergraduate. The principal investigator will also organize a day-long course on advanced memories and architectures leveraging them at a major IEEE conference in the third year of this effort.