Transistor-Based and Voltage-Compatible Nanoscale Memories and Configurable Elements using Phase Transitions

相变导致材料性质的显著变化，并发生在纳米尺度上。铁电、铁磁、超导等都是相变的例子，这些相变是可重复发生的，并被用于小型化设备。另一个不常用的相变现象是金属-绝缘体的相变。无论是在使用中还是在制造中，铁电和金属-绝缘体转变都与电子器件结构非常兼容。这项工作旨在利用一种基于相变现象的新发明来实现10纳米级的非易失性存储器，该存储器能够以纳秒的速度和低功耗获得万亿级的存储密度。这项工作将探索将该组件用作独立存储器和可重新配置，以有效地执行计算任务。该结构利用单个元件(交叉点晶体管)内浮动栅极中的相变现象，在纳秒速度下以1V的工作电压实现滞后特性。这一论断是基于1000纳米量级的S对少数1000纳米量级的S的探索性论证。10纳米的能力将导致集成芯片上的1012位密度。这些存储元件通过控制门被编程，并且可以提供通过功能。这允许非常密集的可编程互连结构，其最简单的形式是用单个相变存储元件替换六晶体管静态随机存取存储器编程元件。这项工作将通过探索尺度、探索新材料作为替代品、发展对潜在现象的理解以及开发使用模型，将单元素相变存储器的初步演示扩展到纳米级。这种存储器本身将是高密度集成系统非常理想的健壮存储介质。这项工作还将探索将这一新元素用作可编程互连元素。这一非常探索性的方向有望通过软件可编程计算取代当前实践的定制设计，其中利用了配置和重新配置计算元件之间的高密度互连的能力。这一部分的努力有可能在功耗和减轻定制和昂贵的设计和生产方面提供重大改进。该提议的智力价值在于，它将探索、开发、理解和展示一种将被普遍使用的纳秒低功率太级存储元件。这项努力还将为通过在纳米级实现快速的芯片可编程性来实现可靠的低成本计算指明新的方向。这一努力的更广泛影响将通过以下方式产生：(A)开发两堂课的教育课堂材料，可将其纳入纳米设备物理学的顶峰课程；(B)纳入两名本科生，一名学生在学年期间来自康奈尔大学，第二名学生在夏季几个月来自康奈尔大学以外的地区，作为本科生研究体验的一部分。首席研究员还将组织为期一天的高级存储器和体系结构课程，在这项工作的第三年的一个重要IEEE会议上利用它们。

Phase transitions result in significant changes in properties of materials and occur down to nanoscale dimensions. Ferroelectric, ferromagnetic, superconductivity, etc. are examples of phase transitions which happen reproducibly and are employed in miniaturized devices. An additional phase transition phenomenon, not as commonly employed, is that of metal-insulator transitions. Ferroelectric and metal-insulator transitions are very compatible with electronic device structures, in use and in fabrication. This work aims to employ a new invention based on phase transition phenomena to achieve 10 nanometer scale non-volatile memory capable of terascale density with nanosecond speeds and low power. The work will explore the use of this component as stand-alone memory and for reconfigurability to efficiently implement computing tasks. The structure employs phase transition phenomena in a floating gate within a single element (a cross-point transistor) to achieve hysteretic characteristics at 1 V of operation at nanosecond speeds. This claim is based on an exploratory demonstration of few 1000?s of nm by 1000?s of nm dimension. The 10 nm capability will lead to 1012 bit density on integrated chips. These memory elements are programmed through control gates and can provide pass functions. This permits a very dense programmable interconnect fabric whose simplest form is the replacement of the six transistor static random access memory programming element by a single phase transition memory element. This effort will extend the preliminary demonstration of the single element phase transition memory to nanoscale by exploring scaling, exploring new materials as replacements, developing the understanding of the underlying phenomena, and developing models for use. Such memories, in themselves, will be a very desirable robust storage medium for highly dense integrated systems. The effort will also explore the use of this new element as a programmable interconnect element. This very exploratory direction holds the promise of replacing custom design, as currently practiced, by software programmable computing where the ability to configure and reconfigure highly dense interconnections between computational elements is utilized. This part of the effort has the potential for providing major improvements in power dissipation and in mitigation of custom and expensive design and production. The intellectual merit of the proposal is that it will explore, develop, understand, and demonstrate a nanosecond low power terascale memory element that will be of universal use. The effort will also point to new directions in achieving reliable low cost computing by implementing fast on-chip programmability at nanoscale. The broader impact of this effort will occur through (a) development of educational class-room material for two lectures that can be incorporated in a capstone course in nanoscale device physics, (b) the inclusion of two undergraduate students, one a student from Cornell during the school year, and the second an under-represented student from outside Cornell during summer months as part of a research experience for undergraduate. The principal investigator will also organize a day-long course on advanced memories and architectures leveraging them at a major IEEE conference in the third year of this effort.