Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Advanced CMOS for Mixed-Mode Systems

PIs建议研究亚100nm制程下CMOS器件、电路和架构的设计，重点是高性能混合信号和射频应用。这项工作的重点将是针对混合模式系统的关键构建模块的器件/电路/架构协同设计。目标是(1)了解深度缩放CMOS的基本器件/电路问题，(2)研究和开发具有新型薄膜材料和新型电路架构的新型器件工程，从而实现更高的速度，功率和噪声性能。近年来，关于将mosfet的尺寸缩小到100nm以下的问题引起了广泛的讨论。诸如替代高k栅极介质、栅极泄漏、浅结形成、源漏扩展工程和通道掺杂工程等主题正在深入研究中。许多基本的器件问题，如短通道效应（DIBL和VTH滚降），断开状态泄漏电流，寄生电容和电阻，以及栅极隧道电流目前正在研究中。显然，50nm以下的晶体管可以实现非常高的性能，主要受串联电阻和电容等寄生因素的限制。难点主要是如何减小关断电流。这主要是由于通道区域和源极/漏极之间的静电耦合。虽然pi可以通过缩放结深来减少耦合，但超浅结意味着高串联电阻和更差的晶体管性能。为了扩大器件设计窗口，克服上述困难，需要探索新的器件结构和新的材料体系。迄今为止，大多数先进器件技术的研究都集中在数字应用上，尽管人们对射频CMOS和用于通信和多媒体应用的高速混合模式电路越来越感兴趣。到目前为止，技术发展还没有充分解决模拟电路所关注的问题。器件模型也不足以进行精确的电路仿真。在这个项目中，他们建议在亚100nm范围内研究CMOS器件、电路和架构的设计，重点是高性能混合信号和射频应用。他们建议研究短通道器件的“模拟非理想性”，例如，门电流、非线性、噪声、固有增益、输出阻抗随漏源电压的变化。SOI上的CMOS已被建议作为150nm以下的大块CMOS的替代方案。在数字应用的情况下，关键的优势可能是在低功耗电路。对于模拟电路，部分耗尽技术与完全耗尽技术的选择仍在争论中。在射频应用的情况下，SOI CMOS的小寄生电容特别有吸引力。但是，与浮体有关的许多问题需要澄清。在这个项目中，pi将研究用于高速模拟电路的SOI mosfet的噪声、频率性能、增益和线性等许多问题。他们还将研究新的50nm以下的器件结构，如SiGe CMOS，低噪声（埋藏通道）CMOS在SOI上，高性能LBJT和DTCMOS。在SiGe的情况下，通过具有较小的带隙SiGe源/漏极区域，减小了内置电势，可以大大减少DIBL和其他短通道效应。此外，更高的迁移率也可以改善源/漏串联电阻。

0120366WooThe PIs propose to investigate the design of CMOS devices, circuits, and architectures in the sub-100nm regime with emphasis on high-performance mixed-signal, and RF applications. The thrust of this work will be device/circuit/architecture co-design targeting critical building blocks of mixed-mode systems. The goals are (1) to understand the fundamental device/circuit issues of deeply scaled CMOS, and (2) investigate and develop novel device engineering with novel thin film materials and new circuit architectures that will enable much superior speed, power, and noise performance.Recently, there is much discussion concerning the scaling of MOSFETs into sub-100nm dimensions. Topics such as alternative high-k gate dielectrics, gate leakage, shallow junction formation, source/drain extension engineering, and channel doping engineering are under intensive investigation. Many fundamental device problems such as short channel effects (DIBL and VTH roll-off), off-state leakage current, parasitic capacitance and resistance, and gate tunneling current are currently being examined. It is apparent that sub-50nm transistors can be realized with very high performance limited primarily by parasitics such as series resistance and capacitance. The challenge is mainly how to reduce the off current. This is fundamentally due to the electro-static coupling between the channel region and the source/drain. Although the PIs can reduce the coupling by scaling the junction depth, the ultra-shallow junction implies high series resistance and worse transistor performance. In order to expand the device-design window and toovercome the above-mentioned difficulties, novel device structures and new material systems need to be explored.So far, most of the advance device technology studies have concentrated on digital applications despite the growing interest in RF CMOS and high-speed mixed-mode circuits for communication and multimedia applications. Until now, technology development does not adequately address the issues of concern to analog circuits. Device models are also not sufficient for accurate circuit simulation. In this project, they propose to investigate the design of CMOS devices, circuits, and architectures in the sub-100nm regime with emphasis on high-performance mixed-signal, and RF applications. They propose to study the "analog nonidealities" of short-channel devices, e.g., gate current, nonlinearity, noise, intrinsic gain, variation of output impedance with the drain-source voltage. CMOS on SOI has been suggested as an alternative to bulk CMOS in sub-150nm regime. In the case of digital applications, the key advantage is probably in low-power circuits. For analog circuits, the choice of partially-depleted technology versus fully-depleted technology is still under debate. In the case of RF applications, the small parasitic capacitance of SOI CMOS is particularly attractive. However, many issues related to the floating body need to be clarified. In this project, the PIs will examine the many issues, such as noise, frequency performance, gain, and linearity of SOI MOSFETs for use in high-speed analog circuits. They will also examine novel sub-50nm device structures such as SiGe CMOS, low noise (buried channel) CMOS on SOI, high-performance LBJT as well as DTCMOS. In the case of SiGe, by having the smaller bandgap SiGe source/drain regions, the built-in potential is reduced and can substantially reduce the DIBL and other short channel effects. In addition, the higher mobilities can also improve the source/drain series resistances.