SBIR/STTR Phase II: A Low Cost Semiconductor Metallization-Planarization Process

这个小型企业创新研究第二阶段项目将建立一个新的电介导的平整技术的市场需求，并定位通过合资企业的市场推出的技术。第二阶段的具体目标是：1。电介导工艺在8英寸晶片上的放大和演示，2。开发特征尺寸1-5至0.17微米及以下的工艺库，以及3.“概念验证”电镀工具的设计。 电镀工具的初步概念设计，包括电介导的过程将由外部公司进行。 可持续的竞争优势与该项目的水平是成本。 与现有技术的铜金属化工艺相比，最小的过度电镀将通过减少铜废浆料来消除或最小化对化学/机械平坦化（CMP）的需要。 这反过来又会消除相关的控制、环境和成本问题。

This Small Business Innovation Research Phase II Project will establish market demand for a novel electrically mediated leveling technology and position the technology for market launch via a joint venture. The specific Phase II objectives are: 1. Scale-up and demonstration of the electrically mediated process on eight inch wafers, 2. Development of a process library for feature sizes 1-5 down to 0.17 microns, and lower, and 3. Design of a "proof of concept" plating tool. Preliminary concept design of a plating tool incorporating the electrically mediated process will be performed by an outside firm. The sustainable competitive advantage associated with the project for leveling is cost. Minimal overplate will eliminate or minimize the need for chemical/mechanical planarization (CMP) by reducing the copper waste slurry compared to the state-of-the-art copper metallization processes. This in turn would eliminate the associated control, environmental, and cost issues.