CAREER: Improving Technology-EDA Integration Through Interconnect Design Tools for Nanometer Design

这项研究计划的目标是探索工具、模型和设计实践，这些工具、模型和设计实践揭示了硅技术与未来EDA工具方向之间的关系。当前的教育、研究、商业半导体和EDA社区的建立方式几乎保证了尖端CMOS技术和最先进的设计自动化之间的知识差距。目前这种知识差距的最好例子是片上电感。这个项目的很大一部分集中在开发模型、指标和设计方法，以评估和改善电感对电路性能的影响。这包括一系列基于rlc的模型，其精度和复杂性各不相同，针对设计流程的不同阶段，从标准单元表征到后期模式全芯片时序。该研究计划正在研究的其他即将出现的知识缺口包括：1)利用可预测性和保持性能的标准单元互连库，以及2)纳米设计（特征尺寸为100纳米）CMOS中继器的可扩展全局信令替代方案。这个职业计划的教育部分有两个广泛的目标：1)尽早和经常向学生介绍片上互连对电路性能的作用，2)通过小组设计项目将不同人群的学生转移到具有相关设计经验的行业。

The goal of this research program is to explore tools, models, and design practices that shed light on the relationship between silicon technology and the direction of future EDA tools. The current education, research, and commercial semiconductor and EDA communities are set up in a way that virtually guarantees a knowledge gap between the cutting edge of CMOS technology and state-of-the-art design automation. The best current example of this knowledge gap is on-chip inductance. A large part of this project focuses on developing models, metrics, and design approaches to assess and ameliorate the impact of inductance on circuit performance. This includes a range of RLC-based models varying in accuracy and complexity that target different stages of the design flow ranging from standard cell characterization to late-mode full-chip timing. Other impending knowledge gaps being studied in this research program include: 1) standard cell interconnect libraries to leverage predictability and maintain performance, and 2) scalable global signaling alternatives to CMOS repeaters for nanometer design (feature sizes 100 nm). The education component of this CAREER program has two broad aims: 1) introduce students to the role of on-chip interconnect on circuit performance early and often, and 2) transfer a diverse population of students to industry with relevant design experience via group design projects.