Reducing Frequency via Speculation and Fall-Back Recovery

Mueller，FrankCCR-0208581”Reducing Frequency via Speculation and Fall-Back Recovery“节能是嵌入式计算中的一个关键问题。 目前，由于嵌入式系统设计人员缺乏应用程序所需的处理速度的详细知识，因此浪费了大量的功率。 朴素的最坏情况下的时序分析夸大了所需的处理器频率，特别是随着软件和硬件复杂度的增加，这项工作提出了一个两层的方法来降低复杂的嵌入式系统的处理器频率。 首先，严格的最坏情况下的时序分析减少了任务消耗的周期数的感知上限。 这降低了最大频率，节省了功率。 其次，架构仿真和具有双频率/电压模式的处理器可实现显著的额外功耗节省。 架构仿真产生近似的最坏情况时序估计，这不一定是安全的，因此是非常低的推测频率的基础。 更高的恢复频率被用作回退模式，以确保由严格的最坏情况下的时序分析，如在第一种方法中提供的安全操作。 这两种方法相辅相成。 与原始方法相比，它们最初显著降低了功耗要求。 此外，它们还通过利用仿真来精确地

Mueller, FrankCCR-0208581" Reducing Frequency via Speculation and Fall-Back Recovery"Conserving power is a key issue in embedded computing. At present, significant power is wasted because embedded system designers lack detailed knowledge of the processing speed needed by applications. Naive worst-case timing analysis exaggerates the required processor frequency, especially as software and hardware complexity increases.This work puts forth a two-tier approach to reduce the processor frequency of complex embedded systems. First, tight worst-case timing analysis reduces the perceived upper bound on the number of cycles consumed by tasks. This reduces the maximum frequency, saving power. Second, architecture simulation and processors with dual frequency/voltage modes enable significant additional power savings. Architecture simulation produces an approximate worst-case timing estimate, which does not have to be safe and, consequently, is the basis for a very low speculative frequency. A higher recovery frequency is utilized as a fall-back mode to ensure safe operation bounded by tight worst-case timing analysis, as delivered in the first approach. These two approaches complement each other. They initially reduce the power requirements by a significant amount when compared with the naive approach. Additionally, they reduce powerrequirements further by exploiting simulation to accurately