Parameterized Model Reduction Techniques for Simulation and Optimization of Mixed-Signal Systems

原型的概念在工程设计中非常普遍；一个人通过构建一个单一的实现，一个原型来调查一个新想法的可行性。无论问题是设计集成电路收发器，基于微机械的缩略图大小的化学试剂探测器，还是飞机，构建原型所需的成本和时间都足以阻碍全面的设计探索。通过取代计算机模型，可以大大减少对物理原型的需求，这一过程被称为计算原型。使用计算原型的承诺是，测试替代设计的便利性将允许设计师检查更激进、更有效的设计替代方案。计算原型的挑战在于开发精确的建模算法和技术，这些算法和技术既灵活又足够快，可以让设计师检查各种设计方案。对于复杂的系统，可能有数百万个相互作用的组件，使用直接数值模拟的计算原型对于设计师在设计探索中使用太慢了。相反，有必要在计算原型中利用层次结构，并且大多数分层计算机验证和优化工具依赖于设计中手动生成的功能块的高级模型。这种“手工”过程耗时且容易出错，并且会干扰新技术的快速部署。由于这个原因，人们对开发从更详细的数值模拟中自动生成准确的高级模型的技术有浓厚的兴趣。在过去的十年中，大量的工作致力于寻找从线性互连和封装中提取高级模型的自动策略。这种努力在非常实际的意义上是成功的，商业计算机辅助公司现在为用户提供了广泛的非常复杂的技术来提取互连的高级模型。芯片设计师不再需要成为信号完整性专家。此外，本研究也大大加深了对模型约简一般问题的认识。正是从这个最近才取得的优势出发，我们现在认为我们可以开始解决接下来的两个问题：生成用于分层优化的参数化降阶模型，以及自动减少与微机械设备或模拟子系统相关的非线性系统。我们最初提出研究非线性模型约简和参数化模型约简的问题。随着预算的减少，我们将只研究非线性模型约简问题，以自动生成微机械设备和模拟子系统的低阶模型。我们将研究涉及平衡实现的非线性推广策略，并将这些策略与轨迹分段线性化相结合，以生成准确的子系统模型。

The notion of prototyping is pervasive in engineering design; one investigates the viability of a new idea by constructing a single implementation, a prototype. Whether the problem is designing an integrated circuit transceiver, a micromachining-based thumbnail-sized chemical agent detector, or an aircraft, the cost and time required toconstruct prototypes is high enough to discourage comprehensive design exploration. It is possible to dramatically reduce the need for physical prototypes by substituting computer models, a process referred to as computational prototyping. The promise of using computational prototyping is that the ease of testing alternative designs will allow designers to examine more radical, and possibility much more efficient, design alternatives. The challenge of computational prototyping is in developing accurate modeling algorithms and techniques which are both flexible and fast enough to allow designers to examine a wide range of design alternatives.For complicated systems, which may have millions of interacting components, computational prototyping using direct numerical simulation is too slow for designers to use in design exploration. Instead, it is necessary to exploit hierarchy in the computational prototype, and most hierarchical computer verification and optimization tools rely on manually generated high-level models for function blocks in the design. This ``by-hand'' process is time-consuming and error-prone, and interferes with rapid deployment of new technology. For this reason, there is strong interest in developing techniques which automatically generate accurate high-level models from more detailed numerical simulation.Over the past decade, substantial effort has been devoted to finding automatic strategies for extracting high-level models from linear interconnect and packaging. This effort was successful in a very practical sense, commercial computer-aided companies now provide users with a wide range of very sophisticated techniques for extractinghigh-level models of interconnect. Chip designers are no longer required to be signal integrity experts. In addition, the research also substantially deepened the understanding of the general problem of model reduction. And it is from this only recently achievedvantage point that we now think we can start to tackle the next two problems: generating {\it parameterized} reduced-order models for use in hierarchical optimization, and automatically reducing the nonlinear systems associated with micromachined devices or analog subsystems. We originally proposed to investigate both the problems of nonlinear modelreduction and parameterized model reduction. With the reduced budget,we will investigate only the nonlinear model reduction problem, to automatically generate low-order models of micromachined devices andanalog subsystems. We will be examining strategies involving nonlineargeneralizations of balanced realizations, and combining such strategieswith trajectory piecewise linearizations to generate accurate subsystemmodels.