Phase-Directed Architecture Optimization and Simulation

阶段导向的架构优化和仿真程序的执行通常表现出随时间变化的行为，其中为应用程序获得峰值性能所需的架构资源可能随时间而显著变化。 我们已经发现，这种随时间变化的行为有一个重复的模式，对于大多数应用程序，这使得程序的执行被分解成阶段，然后我们可以定制一个程序的执行到每个phase.This建议集中在开发有效的运行时架构，捕捉和预测阶段信息。我们将研究如何为电源和能源架构优化创建阶段跟踪和预测架构，以及如何基于跟踪缓存优化的阶段执行硬件代码专业化。通过动态地重新划分处理器中的许多组件（例如，高速缓存、发布和解码宽度、分支预测器），或者基于在应用中看到的阶段行为选择性地使用这些组件的不同实现。 此外，跟踪缓存编译器优化将执行不同的阶段，以利用基于阶段的行为。为了更广泛的影响，我们的阶段分类算法将允许研究人员有效地识别，分类，并预测程序中基于阶段的行为，并使用这些信息来指导他们的基于阶段的硬件，编译器和操作系统的研究。

Phase-Directed Architecture Optimization and SimulationA program's execution typically exhibits time-varying behavior, where architecture resources needed to obtain peak performance for the application can vary significantly over time. We have found that this time-varying behavior has a repetitive pattern for most applications, which allows a program's execution to be broken up into phases, and we can then tailor a program's execution to each phase.This proposal concentrates on developing efficient run-time architectures to capture and predict phase information. We will examine creating phase tracking and prediction architectures for power and energy architecture optimizations as well as to perform hardware code specialization based on phases for trace cache optimizations. Energy consumption can potentially be saved by dynamically re-partitioning many components in a processor (e.g., caches, issue and decode width, branch predictors) on an application specific basis, or selectively using different implementations of these components based upon the phase behavior seen in an application. In addition, trace cache compiler optimizations will be performed for different phases to exploit phase-based behavior.For broader impact, our phase-classification algorithms will allow researchers to efficiently identify, classify, and predict phase-based behavior in programs and use this information to guide their phase-based hardware, compiler, and operating system research.