CAREER: Computer-Aided Design of Mixed ASIC / Reconfigurable Fabrics of the Nanometer Era

提案编号：0347891 INSTITUTION：明尼苏达大学双子城PRINCIPAL调查员：Bazargan，KiaTITLE：计算机辅助设计混合ASIC/可重新配置的纳米Era织物摘要：芯片制造技术的改进带来了电子系统的惊人增长，产生了数十亿赫兹的时钟速度和数十亿门芯片。然而，爆炸性的复杂性、不断上升的制造成本、不断缩短的上市时间窗口以及深亚微米效应正在威胁着电子技术的持续增长。新的系统复杂性导致系统行为的不可靠性(甚至故障)和不可预测性。在SoC中使用类现场可编程门阵列(现场可编程门阵列)可重构模块提高了灵活性，并降低了非循环工程(NRE)成本。嵌入式类FPGA可重构结构已成为当今SoC的一部分，并将不可避免地成为未来设计的一部分，因为它们提供了巨大的优势。然而，在SoC中采用可重构结构的方式存在许多具有挑战性的障碍。这一建议解决了其中的一些挑战：1)提出了不同抽象层次的统计建模和优化，以处理可靠性和可预测性问题。2)研究了可重构织物的结构特点，以降低功耗，改善织物的热传导，同时优化织物的灵活性、成本和性能。3)提出了ASIC/可重构混合结构的计算机辅助设计算法，包括不确定设计的分级评估和估计、低功耗优化和工艺映射，所提出的算法和方法将灵活性、可靠性和生产率作为一等公民考虑进行优化，并与面积、成本和性能等其他设计质量指标一起进行优化。我们将把这项研究的一些成果纳入明尼苏达大学的VLSI课程，以及关于可重构计算的高级课程。此外，还将开发一个网页，其中将包含我们小组和其他研究人员提供的所有课程材料、可重构基准和现场可编程逻辑器件工具。

PROPOSAL NO: 0347891INSTITUTION: U of Minnesota-Twin CitiesPRINCIPAL INVESTIGATOR: Bazargan, KiaTITLE: Computer-Aided Design of Mixed ASIC / Reconfigurable Fabrics of the Nanometer EraAbstract:Improvements in the chip manufacturing technology have brought about astonishing growth of electronic systems, resulting in multi-gigahertz clock speeds and billion-gate chips. However, explosive complexities, rising manufacturing costs, shrinking time-to-market windows, and deep submicron effects are threatening the continuation of the growth in the electronics technology. New system complexities result in unreliability (even failure) and unpredictability of system behavior. Employing FPGA-like (Field Programmable Gate Array) reconfigurable blocks in SoC promotes flexibility and drives non-recurring engineering (NRE) costs down.Embedded FPGA-like reconfigurable fabrics have emerged as part of todays SoC, and will inevitably be part of future designs because of the enormous advantages they provide. However, there are many challenging hurdles in way of employing reconfigurable fabrics within SoC. This proposal tackles a number of these challenges: 1) Statistical modeling and optimization at different levels of abstraction are proposed to take on the reliability and predictability concerns. 2) Architectural features for the reconfigurable fabrics are also investigated to reduce power and improve thermal conduction out of the fabric, while optimizing the flexibility, cost and performance. 3) CAD algorithms for mixed ASIC / reconfigurable fabric are proposed, and include hierarchical evaluation and estimation of uncertain designs, low power optimization and technology mapping.The proposed algorithms and methodologies would consider flexibility, reliability and productivity as first-class citizens to be optimized along with other design quality metrics such as area, cost, and performance. We will incorporate some of the results of this research in the VLSI courses at the University of Minnesota, as well as an advanced course on reconfigurable computing. Furthermore, a web page will be developed that would host all course material, reconfigurable benchmarks and FPGA tools from our group and other researchers.