Cooperative Hardware/Software Designs for Virtual Instruction Set Computers

虚拟指令集计算机的协同软硬件设计[j]。本工作提出了一类协同编译器/微架构技术，可以提高通用处理器的性能，降低其复杂性和功耗。这些被提议的技术的关键特征是它们利用了一个广泛的、特定于实现的指令集接口，在编译器和处理器之间，通过使用虚拟指令集计算机（VISC）架构来实现。VISC架构的特点是具有两个指令集——一个暴露给软件（虚拟ISA或V-ISA），另一个由硬件实际实现（实现ISA或I-ISA）——以及一个转换器，用于透明地用第二个来模拟第一个。因为I-ISA从不向软件公开（除了逻辑上属于处理器设计一部分的特定于实现的转换器），所以它可以自由地公开特定于实现的微体系结构细节和接口，而不必担心跨实现的二进制兼容性。这是构建特定于实现的ISA并将其用于协作编译器/微体系结构技术的机会，这是本提案的中心焦点。建议的工作有两个方面将其与之前关于软件公开架构的工作区分开来。首先，我们从一个丰富的V-ISA层进行翻译，该层保留了程序源代码中存在的许多高级信息。我们假设，这些信息的可用性对于翻译人员转换代码以利用所建议的机制的能力至关重要，并且我们将针对所建议的技术评估这一假设。其次，所提出的技术是真正的协作，因为编译器可以完全了解微体系结构的具体实现细节，而微体系结构可以依赖于编译器的信息和代码生成约束。这使我们的设计充分自由地利用编译器和硬件的独特和互补的优势；两个系统都不是对方的从属。虽然硬件可以有效地观察和响应动态事件，并且可以便宜地推测和验证这种推测，但编译器可以执行全局分析，以减少和简化硬件必须做出的决策，并消除不必要的推测。具体来说，我们建议开发协作编译器技术和微架构，以解决现代通用处理器中的关键挑战。对于这些挑战中的每一个，我们将探索一个或两个广泛依赖于软件交互的技术（在建议中描述），如果没有VISC方法，这些技术将是不切实际的。

AbstractCooperative Hardware/Software Designs for virtual Instruction Set ComputersVikram S. AdveU. of Illinois, Urbana0429561This work proposes a class of cooperative compiler/microarchitecture techniques that can improve performance and reduce the complexity and power-consumption of general-purpose processors. The key feature of these proposed techniques is that they exploit a wide, implementation-specific instruction set interface between the compiler and the processor, enabled by the use of Virtual Instruction Set Computer (VISC) architecture.A VISC architecture is characterized by having two instructions sets - one which is exposed to software (the virtual ISA or V-ISA) and another which is actually implemented by hardware (the implementation ISA or I-ISA)-and a translator that is used to transparently emulate the first with the second. Because the I-ISA is never exposed to software (other than an implementation-specific translator that is logically part of the processor design) it can freely expose implementation specific microarchitectural details and interfaces without concerns for binary compatibility across implementations. It is this opportunity to architect an implementation-specific ISA and use it for cooperative compiler/microarchitecture techniques that is the central focus of this proposal.Two aspects of the proposed work differentiate it from previous work on software-exposed architectures. First, we are translating from a rich V-ISA layer that retains much of the high-level information present in the program's source code. We hypothesize that the availability of this information is fundamental in the translator's ability to transform the code to exploit the proposed mechanisms, and we will evaluate this hypothesis for the proposed techniques. Second, the proposed techniques are truly cooperative, in that the compiler can have full knowledge of implementation-specific details of the microarchitecture, and the microarchitecture can rely on information from and code generation constraints on the complier. This gives our designs full freedom to exploit the distinct and complimentary strengths of compilers and hardware; neither system is the other's subordinate. Whereas hardware can efficiently observe and respond to dynamic events and can cheaply speculate and validate that speculation, the compiler can perform global analysis to reduce and simplify the decisions the hardware has to make and to eliminate unnecessary speculation.Specifically, we proposed to develop cooperative compiler technology and microarchitectures that address critical challenges in modern general-purpose processors. For each of these challenges, we will explore one or two techniques (described in the proposal) that rely extensively on software interaction, and which would be impractical without the VISC approach.