Communication Fabrics for the Globally Asynchronous Network-on-Chip Era

提案编号：0429700参考：密歇根大学安·阿伯德研究人员：密歇根大学研究人员：密歇根州弗林市TITLE：协作研究：全球异步片上网络的通信结构摘要这项研究解决了目前阻碍数字集成系统发展的设计复杂性、功耗以及可靠、高效的信令等关键问题。在数字整合和业绩方面不断取得进展对信息技术的持续发展至关重要。随着集成电路上的晶体管数量达到10亿个大关，当前的单片设计风格和全球同步时钟和信号范例都将失败。复杂性的指数增长导致了设计时间和成本的爆炸性增长。为了实现NSF的社会和经济IT目标，必须在数字集成电路的处理能力、集成度和能效方面做出巨大改进。尽管预计晶体管特征尺寸至少在未来15年内将继续扩大，但功耗、全局信令和时钟已成为阻碍系统性能、效率和集成度提高的关键问题。片上网络范例中的全局异步本地同步(GALS)方案是一个很好的长期解决方案，但这种以通信为中心的方法只有通过一种全新的片上通信方法才能成功。研究人员正在探索利用纳米CMOS的能力进行全球和本地通信的新方案。以通信为中心的片上网络方法给片上通信带来了更大的负担。使用现有技术很难实现异步网络组件之间的健壮通信。现代技术也将达到它们的极限，以提供足够的本地通信。研究人员正在开发一种新的框架，用于在全局(全芯片)和局部(模块内)级别上通过模块化IC进行通信。异步模块之间的全球通信是通过强大且节能的串行链路实现的，而不是传统的并行总线。这项研究还涉及用于本地(模块内)通信和时钟的新电路和互连结构。在较低级别，针对本地和全局信令对线路本身进行研究和优化。

PROPOSAL NO: 0429700INSTITUTION: University of Michigan Ann ArborPRINCIPAL INVESTIGATOR: Flynn, MichaelTITLE: Collaborative Research: Communication Fabrics for the GloballyAsynchronous Network-on-chip EraAbstractThis research addresses the critical problems of design complexity, power consumption, and reliable, efficient signaling that now impede progress in digital integrated systems. Continuing progress in digital integration and performance is vital to the continued development of information technology (IT). As the number of transistors on an integrated circuit reaches the 1 billion mark, both the current monolithic design style and the globally synchronous clocking and signaling paradigm will fail. The exponential growth in complexity is causing explosions in both design time and cost. In order to achieve the social and economic IT goals of the NSF, dramatic improvements must be made in the processing power, integration, and energy efficiency of digital integrated circuits. Although transistor feature size is expected to continue to scale for at least the next fifteen years, power consumption, global signaling, and clocking have become critical problems that now prevent improvements in system performance, efficiency, and integration. The globally asynchronous locally synchronous (GALS) scheme within a network-on-chip paradigm is a good long-term solution, but this communications-centric methodology can only succeed with a fundamentally new approach to on-chip communication. The investigators are exploring new schemes for global and local communication that take advantage of the capabilities of nanometer CMOS. The communications-centric network-on-chip approach places a far greater burden on on-chip communication. Robust communication between asynchronous network components is difficult using present techniques. Modern techniques will also be stretched to their limits to provide adequate local communication. The investigators are developing a new framework for communication across a modular IC, at both the global (full chip) and local (intra-module) levels. Global communication between asynchronous modules is achieved with robust and power efficient serial links instead of traditional parallel buses. This research also concerns new circuit and interconnect structures for local (intra-module) communications and clocking. At a lower level, wires themselves are studied and optimized for both local and global signaling.