Generating High-Quality Complex Digital Systems from High-Level Specifications

【摘要】CMOS技术的商业化发展使我们有可能在2010年拥有5000万gatesic。只有当EDA工具能够跟上不断增长的尺寸和设计的复杂性时，这种大型asic才会普及。虽然这个问题被广泛认识，但大多数商业研究和开发工作都集中在半导体工艺相关问题和低级设计工具上，而不是高级设计工具。拟议的研究将开发一种高级设计方法和配套工具，以减少设计工作量，将复杂的数字系统转化为高质量的物理实现。任何此类方法的中心主题都必须是构建的正确性和快速透明的性能调优。研究人员将以麻省理工学院和其他地方的工作为基础，从高级硬件描述合成为受保护的原子动作。这项先前的工作构成了Bluespec硬件描述语言的基础，该语言由Bluespec Inc.开发，作为SystemVerilog的扩展，用于硬件建模、综合和验证。研究人员将使用Bluespec工具作为开发新的设计方法、合成算法和工具的基础设施。研究将集中在两个具体领域。性能规范和相关的综合算法：目前，Bluespeccompiler可以推导出一个很好的调度，满足在被保护的原子动作中检测到的调度约束。尽管自动生成的控制逻辑能够通过构造方法实现功能上的正确，但实现足够的性能有时是具有挑战性的。这个项目将开发一些方法，允许设计人员直接指定规则和模块接口的并发性属性，并让编译器生成一个实现，在不违反正确性的情况下保留期望的并发性。单元事务级（Unit Transaction Level， UTL）规则：给定具有深度嵌套模块层次结构的设计，Bluespec编译器可以生成任意复杂的控制结构和长连接。该项目将开发单元事务级别（Unit Transaction Level， UTL）规则，将其强加于受保护的原子操作之上，以便能够在硬件中有效地实现非常大的设计。UTL规则依赖于延迟不敏感的接口，允许在合成后插入额外的寄存器，以帮助定时关闭和降低功耗。UTL规范使设计师能够更清楚地看到高级设计决策将如何影响各种物理设计问题。

Abstract0541164ArvindMITGenerating High-Quality Complex Digital Systems from High-Level Specifications Commercial developments in CMOS technology make it likely that we will have 50 million-gateASICs by 2010. Such large ASICs will be commonplace only if the EDA tools can keep up with thegrowing size and complexity of designs. Though this problem is widely recognized, most commercialresearch and development efforts have focused on semiconductor process related issues and low-level design tools as opposed to high-level design tools. The proposed research will develop a high-level design methodology and accompanying tools to enable complex digital systems to be translated into high quality physical implementations with reduced design effort. The central themes of any such methodology must be correctness by construction and rapid and transparent performance tuning. The researchers will build upon the work at MIT and elsewhere on synthesis from high-level hardware descriptions expressed as guarded atomic actions. This prior work forms the basis of the Bluespec hardware description language which has been developed by Bluespec Inc. as an extension to SystemVerilog for hardware modeling, synthesis, and verification. The researchers will use Bluespec tools as infrastructure for developing new design methodologies, synthesis algorithms, and tools. The research will focus in two specific areas.Performance specifications and associated synthesis algorithms: Currently the Bluespeccompiler deduces a good schedule that satisfies the scheduling constraints detected amongthe guarded atomic actions. Although the automatically generated control logic enables afunctionally correct by construction methodology, achieving adequate performance can sometimesbe challenging. This project will develop methods to allow designers to directly specifythe concurrency properties of rules and module interfaces and have the compiler generate animplementation that preserves the desired concurrency without violating correctness. Unit Transaction Level (UTL) discipline: Given a design with a deeply nested module hierarchy, the Bluespec compiler can generate arbitrarily complex control structures and long wires. The project will develop the Unit Transaction Level (UTL) discipline to be imposed on top of guarded atomic actions so that very large designs can be implemented effciently in hardware. The UTL discipline relies on latency-insensitive interfaces to allow additional registers to be inserted post-synthesis to aid in timing closure and power reduction. The UTL discipline enables designers to more clearly see how high-level design decisions will impact various physical design issues.