SBIR Phase I: Optical Motherboards with Nano-Second Memory Bus Latency enabled by CMOS-Compatible Inter-Chip Optical Communications Platform

这个小型企业创新研究（SBIR）第一阶段项目将产生一个具有纳秒级延迟时间的计算机总线系统，并增强总线带宽。计算机速度的快速增长是由不断增加的设备密度和计算速度推动的。然而，完全实现不断增长的计算机能力的主要障碍是无法提高芯片间的通信速度，在过去的十年中，芯片间的延迟时间一直保持在30ns左右。在现代计算中，主要的性能限制因素已经成为与连接快速CPU和内存芯片的主板数据总线相关的长延迟时间。因此，随着CPU和内存芯片速度越来越快与主板数据总线速度越来越慢之间的差距越来越大，数据传输已经成为主要的性能限制因素。如今，许多重要的高端应用程序对内存访问性能非常敏感。为了缓解总线速度慢的问题，当今的计算机体系结构设计者不得不开发越来越复杂的存储子系统，例如增加分层缓存级别和设计复杂的预取机制，从而牺牲芯片尺寸、性能和成本。依靠不受电容和电阻阻碍（减慢）的光速，这种芯片间光总线平台将显著降低目前存储器总线延迟（通信速度），从大约30纳秒减少至少30到1纳秒，从而消除存储器访问瓶颈。

This Small Business Innovation Research (SBIR) Phase I project will result in a computer bus system with nanosecond latency time in addition to enhanced bus bandwidth. The rapid growth in computer speed is fueled by the increasing device density and computing speeds. However, a major roadblock to fully realizing the increasing computer power has been the inability to increase inter-chip communication speeds, the inter-chip latency time has remained constant at about 30ns for the past decade. The dominant performance limiting factor in modern computing has become the long latency time associated with the mother board data bus connecting the fast CPU and memory chips. As a result, with the increasing gap between the ever-increasing fast CPU and memory chip speeds and the slow mother board data bus speeds, data transfer has become the dominant performance limiting factor. Many important high-end applications today are extremely sensitive to memory access performance. As a way to alleviate the slow bus problem, computer architecture designers today are forced to develop more and more complex memory subsystems, such as adding hierarchical cache levels and designing complicated pre-fetching mechanisms, sacrificing chip size, performance and cost. Relying on the speed of light, which is not encumbered (slowed down) by electrical capacitances and resistances, this inter-chip optical bus platform will significantly reduce present memory bus latency (communication speed) from around 30 nano-seconds by at least a factor of 30 to 1nano-second, thus removing the memory access bottleneck.