SBIR Phase II: Ultra-high Throughput Parallel Optical Links for Chip-to-Chip Interconnects

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The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to create very low power and very high capacity optical interconnects for general computer applications. Computer performance is limited by the speed, power, and latency of connections between chips and memory. The limitations of electrical interconnects are well known, and optical interconnects overcome the limitations and offer 100-1000 times performance improvements. While historically optical interconnects have been hampered by high cost and high power, recent developments show that the promise of optical interconnects can be practically realized. Optical interconnects will dramatically improve overall performance of enterprise and cloud computing services, especially when used in data center computers, while reducing electrical power consumption. This will in turn permit a vast improvement in resource utilization and dramatic reduction in the cost of computation across all segments of societyThe proposed project will develop an optical peripheral component interconnect expreess (PCIe)-compatible transparent bridge for general computer interconnects. PCIe is the most prevalent interconnect used today in computers. The technology developed in this proposal, based on light emitting diode (LED)-based transmitters, multicore optical fibers, and complementary metal-oxide semiconductor (CMOS)-compatible photodetectors, seeks to reduce electrical power consumption from ~10 pJ/bit for electrical solutions to ~100-200 fJ/bit. The use of LEDs leverages investments already made for cost and power effective LED lighting and displays. The small size of the LEDs and multicore fibers allows for data densities of 1 Pbps/cm2. Electrical interconnects and other optical interconnect technologies cannot compare with the performance of these LED based optical interconnects. These advantages enable physical disaggregation of the compute, storage, and memory functions, improving system performance and resource utilization. This Phase II effort is focused on the development of a PCIe-compliant transparent bridge for applications in chip to chip and chip to memory interconnects.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.