CAREER: Hardware/Software Support for Probabilistic Architectures

该研究项目研究了在极端制造变化和现场硬故障下设计和管理多核处理器资源的模型和方法，预计将在不久的将来的技术世代中实现。这些现象受概率定律的支配，可以通过处理潜在不确定性的方法来适当地处理。协同的硬件和系统软件元素在通过设计预测、资源供应、自我发现和自主管理实现这些目标方面发挥着核心作用。将设计硬件以支持适应和现场监测。系统软件将读取原位传感器，应用统计推断，并使用在线学习策略来建立有关片上资源的运行时知识。这些知识将用于优化处理器的性能、功率和可靠性。制造变化和操作压力将使原始技术的规模化越来越困难，并将潜在地限制计算在十亿晶体管时代的商业和社会影响。本研究通过设计和管理高效、可靠的多核处理器来解决这些挑战。该项目将通过对研究生的研究训练和将研究成果纳入现有的本科和研究生课程，对教育产生影响。代表性不足群体的成员将受益于指导工作，并将积极参与研究。

This research project investigates models and methodologies for designing and managing multi-core processor resources under the extreme manufacturing variations and in-field hard failures projected for near future technology generations. These phenomena are governed by laws of probability and can be appropriately handled by methods that address the underlying uncertainty. Synergistic hardware and system software elements play a central role in achieving these goals through design forecasting, resource provisioning, self-discovery, and autonomic management. Hardware will be designed to support adaptation and in-field monitoring. System software will read in situ sensors, apply statistical inference, and use on-line learning strategies to build run-time knowledge about on-chip resources. This knowledge will be used to tune the processor for performance, power, and reliability.Manufacturing variation and operational stress will make it increasingly difficult to benefit from raw technology scaling and will potentially limit the commercial and societal impact of computing in the billion transistor era. This research addresses these challenges by enabling the design and management of efficient, reliable, multi-core processors. This project will have educational impact through research training of graduate students and incorporation of research findings into existing undergraduate and graduate courses. Members of underrepresented groups will benefit from mentoring efforts and will be active participants in research.