SHF: Small: Integrating Compiler and Architecture Design to Boost Timing Speculation

SHF：小型：集成编译器和架构设计以促进时序推测

• 批准号: 1116610
• 负责人: Russell Joseph
• 金额: $ 49.34万
• 依托单位: Northwestern University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-09-01 至 2016-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1116610&HistoricalAwards=false
• 关键词: SHF; Small; Integrating; Compiler; Architecture

This project examines the art and science of co-designing compilers and hardware for circuit-level timing speculation thereby enabling reliable, high-performance computer systems. Timing speculation, an exciting, forward-looking hardware design alternative, allows designers to abandon pessimistic design guidelines and consequently extract more performance from the silicon. Unfortunately, timing speculation has been under-served by contemporary compiler technologies. This research develops novel design paradigms that allow the compiler and architecture to be jointly optimized to build highly effective timing speculative systems, a significant industrial and societal benefit. Outreach efforts motivate students to pursue graduate study in computer science and engineering. Given the promise of timing speculation but the prevailing downward focus of existing work, targeted code generation addresses neglected portions of the system stack and offers enticing possibilities. This research develops timing-aware compilation that applies instruction-level error rate models to analyze and optimize instruction sequences. By generating binaries specifically targeted for timing speculation, the compiler aims to significantly reduce incidence of timing errors which demand dynamic correction. This extends the reach of timing speculation by reducing recovery cost. This allows systems to operate at higher clock frequencies or enables better energy-efficiency through lower supply voltages. The research develops compact timing error rate models through machine learning techniques and determines how existing flow analysis present in modern compilers could be used to drive these error rate models. The compiler extends existing code optimizations to include the estimated impact of timing errors generated during analysis phases. The compiler technology is being used to examine new design paradigms for integrated timing speculative systems which include co-designed and co-optimized architectures and compilers.

这个项目考察了为电路级时序推测共同设计编译器和硬件的艺术和科学，从而使可靠、高性能的计算机系统成为可能。时序推测是一种令人兴奋的、前瞻性的硬件设计替代方案，允许设计人员放弃悲观的设计指导方针，从而从硅中提取更多性能。不幸的是，当代编译器技术未能充分满足计时推测的需要。这项研究开发了新的设计范例，允许编译器和体系结构联合优化，以构建高效的计时推测系统，这是一项显著的行业和社会效益。外展工作激励学生攻读计算机科学和工程方面的研究生课程。考虑到时间推测的前景，但现有工作的主流向下重点，目标代码生成解决了系统堆栈中被忽视的部分，并提供了诱人的可能性。这项研究开发了时序感知编译，它应用指令级错误率模型来分析和优化指令序列。通过生成专门针对计时推测的二进制文件，编译器旨在显著减少需要动态校正的计时错误的发生率。这通过降低回收成本扩大了时机投机的范围。这使得系统能够以更高的时钟频率运行，或者通过更低的电源电压实现更高的能效。这项研究通过机器学习技术开发了紧凑的计时错误率模型，并确定了如何使用现代编译器中现有的流分析来驱动这些错误率模型。编译器扩展了现有的代码优化，以包括在分析阶段生成的计时错误的估计影响。编译器技术正被用于检查集成定时推测系统的新设计范例，其中包括共同设计和共同优化的体系结构和编译器。