Yield and Reliability Enhancement for On-Chip Multicore Memories in Nanoscale Technology

随着计算机系统的出现，在一个芯片上有几个处理器核心(称为？多核芯片？)带来了在低成本台式计算机上从未体验过的高性能。对于日常用户来说，大量计算能力的可用性将在许多领域提供好处，包括科学、消费者和商业，因为可以创建和使用更复杂的应用程序。计算密集型应用程序，如制药开发、科学模拟和财务预测可以在台式计算机上运行，从而提供对这些重要应用程序的结果的更快和更便宜的访问。然而，用于未来具有数百个处理器的多核芯片的小尺寸晶体管将使计算机系统异常脆弱。由于晶体管体积小，在芯片制造过程中更难以避免引入缺陷和操作特性的变化。这些缺陷和变化可能导致硬件故障。这个问题在用于实现片上存储器的晶体管器件中尤为明显。由于多核芯片将有数亿个存储晶体管，因此很可能某个特定芯片无法正常运行。事实上，功能齐全的芯片将会很少，由于它们的稀缺性，它们将会很昂贵。如果未来的多核芯片要实现其对低成本桌面计算的承诺，就必须解决内存故障带来的障碍。本研究提出了？柔软的收益率,?在芯片制造过程中存在缺陷和操作变化，但在芯片部署后几乎可以修复。基于软良率，提出了一种新的方法，称为测试和连续自适应修复（T-CAR），以减轻缺陷和操作变化对存储晶体管的影响。T-CAR通过识别导致故障的条件并修复内存来解决这些条件，从而为故障的内存组件制定计划。该方法通过在软件应用程序运行时重新配置硬件来进行修复，以避免损害应用程序性能。这项研究的智力影响将是开发新的测试和修复算法，硬件修复机制，以及评估软产量效益的模型和指标。更广泛的社会影响是开发更有能力、更可靠和更低成本的系统，这将导致消费、商业和科学应用的新类别。该项目还将培养博士研究生，使他们成为未来的教育工作者、科学家和工程师，以应对新出现的可靠性问题。

With the emergence of computer systems that have several processor cores on a single chip (called a ?multicore chip?) comes the promise of high-performance never before experienced on a low-cost desktop computer. The availability of massive computing horsepower to everyday users would provide benefits in many domains, including scientific, consumer, and business, as more sophisticated applications could be created and used. Computationally intensive applications such as pharmaceutical development, scientific simulation, and financial forecasting could be run on a desktop computer, providing faster and cheaper access to the results of these vital applications. However, the small size of the transistors that will be used in future multicore chips with hundreds of processors will make the computer system exceptionally fragile. With small transistors, it becomes more difficult to avoid introducing defects and variations in operational characteristics during chip manufacturing. These defects and variations can cause hardware failures. This problem is particularly pronounced in transistor devices used to implement on-chip memory. Because a multicore chip will have hundreds of millions of memory transistors, it is likely that a particular chip may not operate correctly. Indeed, there will be few fully functional chips, which will be expensive due to their scarcity. If future multicore chips are to attain their promise for low cost desktop computing, the obstacles posed by failures in memory must be addressed. This research proposes the new concept of ?soft yield,? where defects and operational variations remain during chip manufacture, but are virtually repaired after chip deployment. Based on soft yield, a novel approach, called Test and Continuous Adaptive Repair (T-CAR), is proposed to mitigate the impact of defects and operational variations in memory transistors. T-CAR plans for failed memory components by identifying the conditions that lead to failure and repairing the memory to account for those conditions. The approach makes repairs by reconfiguring the hardware as a software application runs to avoid harming application performance. The intellectual impact of this research will be to develop new test and repair algorithms, mechanisms for hardware repair, and models and metrics to evaluate the benefit of soft yield. The societal broader impact is to develop more capable, reliable and lower cost systems, which will lead to a new class of consumer, business and scientific applications. The project will also train Ph.D. graduate students to serve as future educators, scientists and engineers equiped to deal with this emerging reliability problem.