Cross-Layer Error Exploitation for Next Generation SoCs

ID：0702797标题：下一代SoC的跨层错误利用PI名称：Nik dutPI Inst：UC IrvineAbstractToday‘s Communications Appliance(例如，掌上电脑电话、全球定位系统等)是通信、视频、图像和语音等多种技术的综合。这些技术的共同点是，它们(无论是通过设计，还是通过其固有的性质)都表现出了对错误的弹性。例如，用户几乎不会注意到图像或视频中的暗像素。另一方面，当无线传输信息时，预计会在空中发生错误，并且接收器被设计为纠正此类错误。相比之下，今天的芯片被设计成没有错误，那些有不可修复缺陷的芯片被丢弃。虽然先进的半导体制造技术允许在小芯片尺寸下制造更复杂的片上系统(SoC)，但由于单位面积上有大量晶体管以及它们之间的接近，实现100%无错误的芯片设计在经济上是不现实的。对于移动应用程序，从100%正确的模式转变不仅是可行的，而且似乎是不可避免的。该项目的成果将产生一种结构化和科学的方法，以利用复杂SoC的多个抽象级别的错误意识。传统不同(抽象级特定)技术的整体集成将使系统设计人员能够快速探索复杂的芯片实现，以满足广泛的功率、性能和成本属性。从长远来看，该项目将对生产者-消费者链的两端产生积极影响：芯片制造公司将通过允许高效制造移动芯片来提高他们的生产率和竞争力；消费者将通过更低成本的移动芯片受益，这种芯片允许他们的移动设备运行更长时间，同时确保新兴应用程序的安全和正确执行。

ID: 0702797 Title: Cross-Layer Error Exploitation for Next Generation SoCs PI name: Nik DuttPI Inst: UC IrvineAbstractToday's communication appliances (e.g., PDA phones, GPS units, etc.) are a synergy of many technologies such as communication, video, image, and voice. What is common among these technologies is the fact that they exhibit (either by design, or by their intrinsic nature) a resiliency to errors. The user will hardly notice, for example, a dark pixel in an image or a video. When transmitting information wirelessly, on the other hand, errors are expected to occur over the air and receivers are designed to correct for such errors. By contrast, today's chips are designed to be error free and those chips that have non-fixable defects are discarded. While advanced semiconductor manufacturing technologies allow the fabrication of ever more complex Systems-on-Chip (SoCs) in small die sizes, it becomes economically impractical to achieve a 100% error-free chip design due to the large number of transistors per unit area as well as their proximity. For mobile applications, a paradigm shift away from 100% correctness is not only feasible, but seemingly unavoidable. The outcome of this project will result in a structured and scientific approach to exploit error-awareness across multiple abstraction levels of complex SoCs. A holistic integration of traditionally disparate (abstraction-level specific) techniques will allow system designers to rapidly explore complex chip implementations to meet a wide range of power, performance, and cost attributes. In the long term, this project will positively impact both ends of the producer-consumer chain: chip manufacturing companies will improve their productivity and become more competitive by allowing efficient fabrication of mobile chips; and consumers will benefit through lower cost mobile chips that allow longer operation of their mobile appliances while ensuring safe and correct execution of emerging applications.