U.S.-Egypt Cooperative Research: A Novel Flash Fast-Locking Wide-Band Digital Phase-Locked Loop

描述：该项目支持加州州立大学长滩分校电气工程系马哈茂德·瓦格迪博士的合作研究。埃及的合作者是埃及开罗电子研究所的Hamed El-Simary博士。他们计划研究一种新型的闪存快速锁定宽带数字锁相环(DPLL)。有许多应用(通信、工业等)它们在速度和吞吐量方面对信息技术产生了重大影响。这些应用是GHz频段的射频(RF)应用，因此需要快速锁定的数字锁相环(DPLL)。该研究将提供一种工作在GHz范围(2 GHz)的新型快速锁定数字锁相环，它采用0.18微米的CMOS工艺，比其他技术如SiGe、Bipolal等更便宜。项目目标包括：(1)比较研究各种快速锁定数字锁相环的应用：一种实现快速收敛的数学算法，改变电荷泵(CP)收敛速度的非线性特性，用CP和PFD(鉴相器)反馈，或电流模式技术；现有文献包括数十篇论文和专利，而不是像传统的数字锁相环那样数千；该研究将使用诸如SIMULINK、Verilog和/或VHDL语言的行为建模工具，(2)设计(使用Cadence/Mentor Graphics)所提出的新型快速锁定DPLL，其包括两个阶段：基于闪存(并行)算法的粗调阶段，随后类似于传统DPLL的微调阶段，(3)用于评估相对于其他技术的优势的时序分析，利用实际硬件延迟推导出锁定时间的闭式公式，以及通过行为建模进行锁定时间分析，(4)减少以下各项：锁定时间、频率超调、相位噪声(抖动)、虚假信号、(5)研究数字锁相环的稳定性(通过Simulink)、寄生感知、射频问题等(通过安捷伦ADS软件)，以及(6)制造和硬件测试。智力优势：这项研究将填补相对较新的数字快速锁相环领域的一些空白。它将通过数学和行为建模技术更全面地了解这些DPLL的不同类别之间的差异。特别是，这项研究将为计算锁定时间提供完整的量化基础，包括封闭形式的公式，锁定时间是许多重要应用的关键性能参数。该方案提出了一种使用闪存算法的新型宽带DPLL，该算法在概念上类似于闪存A/D转换器所使用的算法；该算法与许多快锁DPLL所采用的较慢的逐次逼近算法相对应。广泛的影响：由于手机、扩频通信、信息技术和时钟/数据恢复(CDR)电路对快速锁定DPLL的需求，这项研究将使私营行业、航天机构和整个社会受益。该项目将支持研究生参与这一国际合作项目。该项目得到了美国-埃及联合基金计划的支持，该计划为两国的科学家和工程师提供资助，以开展这些合作活动。

0710887WagdyDescription: This project supports collaborative research by Dr. Mahmoud Wagdy, Department of Electrical Engineering, California State University-Long Beach. The Egyptian collaborator is Dr. Hamed El-Simary at the Electronics Research Institute, Cairo, Egypt. They plan to investigate a novel flash fast locking wide-band Digital Phase-Locked Loop (DPLL). There are many applications (communications, industrial, etc.) which significantly influence information technology insofar as speed and throughput are concerned. These applications are Radio Frequency (RF) ones in the GHz frequency range, and thus require fast-locking digital phase-locked loops (DPLLs). The research will provide a working novel fast-locking DPLL in the GHz range ( 2 GHz) using 0.18 microm CMOS process, which is cheaper than other technologies such as SiGe, Bipolar, etc. The project objectives include: (1) a comparative study of various categories of fast-locking DPLLs employing: a mathematical algorithm to achieve fast convergence, nonlinear characteristics for the CP (charge pump) to change the convergence rate, feedback with the CP and PFD (phase frequency detector), or current-mode techniques; the existing literature includes tens of papers and patents, not thousands as in conventional DPLLs; the study will employ behavioral modeling tools such as Simulink, Verilog and/or VHDL, (2) designing (using Cadence/Mentor Graphics) the proposed novel fast-locking DPLL comprising two stages: a coarse-tuning stage based on a flash (parallel) algorithm, followed by fine-tuning stage similar to conventional DPLLs, (3) timing analysis to assess advantages over other techniques, derivation of closed-form formulae for lock time using actual hardware delays, as well as lock time analysis via behavioral modeling, (4) reduction of the following: lock time, frequency overshoot, phase noise (jitter), spurious signals, and static noise errors due to mismatches in PFD/CP, (5) investigating DPLL stability (via Simulink), parasitic awareness, RF issues (via Agilent ADS software), etc., and (6) fabrication, and hardware testing.Intellectual Merit: This research will fill a number of voids in the relatively recent field of digital fast-locking phase-locked loops. It will provide more complete understanding of the differences between various categories of these DPLLs via mathematical and behavioral modeling techniques. In particular, the research will provide a complete quantitative basis including closed-form formulae, for computation of the lock time, which is a critical performance parameter for many important applications. The proposal presents a novel wide-band DPLL using a flash algorithm, which is conceptually similar to the one employed by flash A/D converters; this algorithm is the counterpart of the slower successive-approximation algorithm employed by many fast-locking DPLLs.Broader Impacts: Because of the need for fast-locking DPLLs for cellular phones, spread-spectrum communications, information technology, and clock/data recovery (CDR) circuits, this research will benefit private industry, space agencies, and the society at large. The project will support graduate students for working on this international cooperative project. This project is being supported under the US-Egypt Joint Fund Program, which provides grants to scientists and engineers in both countries to carry out these cooperative activities.