CPA-DA: Low Power Asynchronous Circuits from Traditional Clocked Verilog and ASIC CAD

项目ID：0818408标题：传统计时Verilog和ASIC CADInst：UtahPI大学名称：Ken StevensABSTRACT异步设计与传统计时设计相比，已被证明为各种设计提供了实质性的功率和性能优势。这一优势延长了电池寿命并提高了能效。然而，异步设计(无时钟设计或？握手时钟？)由于与传统计时CAD和设计方法不兼容，它仍然是一项奇异的技术。采用异步设计方法的一个基本问题是无法通过静态时序分析来表征和预测性能，并使用时序驱动的功率/性能优化来布局和布线这些设计。这项建议开发了解决这一障碍的基本技术，从而使异步设计能够集成到时钟设计和时钟CAD工具流中。这为设计提供了广泛的能力，使其能够以更高的性能运行并变得更节能。这项工作基于一种名为相对计时的新技术，该技术使用形式验证技术来证明异步模板的计时和行为正确性。计时现在被表示为逻辑约束。这些逻辑约束被用来将循环时序电路分解成有向无环图(DAG)。这些设计现在作为.sdc限制在时钟设计和工具流中得到直接支持。目前，这项技术的专业知识非常有限，因此培训学生必须主要在大学提供，而不是在工作中。缺乏工业专业知识和这种突破性方法的高潜力相结合，导致了业界的极大兴趣。全球最大的半导体公司英特尔和全球最大的两家设计自动化公司之一Synopsys都在提供资金和指导，以帮助将该项目商业化和技术转让。一家初创公司Nanochronous正在提供CAD工具和研究协作。少数族裔的参与也是该项目的一个重点，因为这项研究将支持一名女工程师。将成立一个讲习班来传播这项工作的成果。最后，该项目将与开发片上网络技术的姊妹基金合作，以证明将这项工作应用于更广泛应用的简单性。

Project ID: 0818408Title: Low Power Asynchronous Circuits from Traditional Clocked Verilog and ASIC CADInst: University of UtahPI name: Ken StevensABSTRACTAsynchronous design has been shown to provide substantial power and performance advantages to a wide range of designs when compared to traditional clocked design. This advantage results in extended battery life and energy efficiency. However, asynchronous design (clockless design or ?handshake clocking?) has remained an exotic technology due to its incompatibility with traditional clocked CAD and design methodologies. A fundamental problem to adoption of asynchronous design methods is the inability to characterize and predict performance through static timing analysis, and use timing driven power/performance optimization to place and route these designs. This proposal develops fundamental technology that resolves this roadblock, thus enabling asynchronous design to be integrated into clocked designs and into the clocked CAD tool flows. This opens up a broad capability for designs to operate at higher performance and become more energy efficient. This work is founded on a novel technology called relative timing which uses formal verification techniques to prove both timing and behavioral correctness of asynchronous templates. Timing is now represented as logical constraints. These logical constraints are used to break cyclical sequential circuits into directed acyclic graphs (DAGs). These designs are now directly supported in clocked designs and tool flows as .sdc constraints.There is currently very limited expertise in this technology, so training students must primarily be provided at the university rather than on the job. The combination of a lack of industrial expertise and the high potential of this breakthrough approach has resulted in significant industrial interest. Both Intel, the worlds largest semiconductor firm, and Synopsys, one of the worlds top two design automation companies, are providing funding and mentorship to help commercialize and technology transfer this project. Nanochronous, a startup, is providing CAD tools and research collaboration. The involvement of under represented minorities are also a focus of this project as a female engineer will be supported by this research. A workshop will be formed to disseminate the results of this work. Finally this project will work collaboratively with a sister grant developing Network-on-Chip technology to prove the simplicity of adopting this work into broader applications.