SBIR Phase II: A New Class of Fast Fourier Transforms

该小型企业创新研究（SBIR）第二阶段项目旨在开发用于嵌入式信号处理集成电路的高性能可编程快速傅立叶变换（FFT）电路。在过去的40年中，用于执行并行FFT实现的技术保持相对不变，基本上基于信号流图及其映射的不同排列。现在，性能的提高主要是通过根据摩尔定律缩小电路几何尺寸来实现的。由于集成电路制造的物理学所施加的限制，预期信号处理的持续改进将仅通过与先进集成电路技术组合的更有效算法实现来实现。该建议侧重于一个完全不同的架构，并行FFT电路的基础上，一个新的矩阵制定的离散傅里叶变换（DFT），以实现这一目标。这种新公式的具体优点包括：1）逻辑和存储器资源需求减少; 2）消耗更少的功率; 3）产生显著的附加功能;以及4）设计、测试和维护工作减少，因为电路简单、局部连接和结构化。该项目的成果是基于SBIR第一阶段开发的可行性原型的商业质量FFT电路。DFT子系统是大量实时通信、雷达、医疗、声学、导航、监视、遥感和机器人检测应用的关键和重要组成部分，可以说是所有信号处理算法中最突出的。因此，更多功能、更高效和更高性能的FFT的可用性将显著提高许多电子产品的功效。这种新的FFT技术的好处将最适合移动的无线设备，这是电子产品最大和增长最快的市场，因为未来的4G无线协议将基于正交频分复用，这是一种利用FFT的方案。因此，未来的大多数无线设备将使用嵌入式FFT电路。然而，与当今的无线移动的设备相比，支持4G通信要求的计算需求将增加约10倍。因此，将需要FFT的更有效的集成电路实现以继续保持移动的电器的成本和功率使用低。

This Small Business Innovation Research (SBIR) Phase II project is directed at development of a high performance, programmable fast Fourier transform (FFT) circuit for use in embedded signal processing integrated circuits. Over the last 40 years the technology for executing parallel FFT implementations has remained relatively unchanged, being based essentially on different permutations of the signal flow graph and mappings thereof. Performance improvements are now largely achieved by shrinking circuit geometries according to Moore's Law. Because of the limits imposed by physics of integrated circuit fabrication, it is expected that continued improvement in signal processing will only be achieved with more efficient algorithmic implementations in combination with advanced integrated circuit technologies. This proposal focusses on a radically different architecture for parallel FFT circuits based on a new matrix formulation of the discrete Fourier transform (DFT) to achieve exactly this goal. The specific advantages of this new formulation include: 1) logic and memory resource requirements are reduced; 2) less power is consumed; 3) significant added functionality is accrued; and 4) design, test, and maintenance efforts are diminished because the circuits are simple, locally connected and structured. The outcomes of this project is a commercial quality FFT circuit based on the feasibility prototypes developed during SBIR Phase I.The DFT sub-system is a critical and important component of large number of real-time communications, radar, medical, acoustics, navigation, surveillance, remote sensing, and robotic inspection applications and is arguably the most prominent of all signal processing algorithms. Consequently, the availability of more functional, efficient, and higher performance FFTs will significantly improve the efficacy of a host of electronic products. The benefits of this new FFT technology would be best suited to mobile wireless devices, the largest and fastest growing market for electronic products, because future 4G wireless protocols will be based on orthogonal frequency division multiplexing, which is a scheme that makes use of the FFT. Consequently, most wireless devices of the future will use embedded FFT circuitry. However, the computational demands to support 4G communication requirements will increase by a factor of ~10 compared to today's wireless mobile devices. Therefore, more efficient integrated circuit implementations of FFTs will be required to continue to keep the cost and power usage of mobile appliances low.