Injection-Locked Clock Distribution System

本研究的目标是为下一代高速片上系统（如高性能多核微处理器）开发一种新的时钟系统，以克服传统时钟在时序、噪声和功耗方面面临的根本挑战。在所提出的时钟方案中，全局时钟分布在整个芯片上，然后由注入锁定振荡器在本地再生。该方法基于非线性电路技术、注入锁定以及系统、设备和物理方面的全套支持技术。智力优势：该项目将推进对集成系统中时序不确定性的理解，研究注入锁定时钟的潜在挑战，并开发多层次（器件，电路和系统）技术来解决这两个问题。与传统时钟相比，所提出的时钟方案可以提供显著的功耗节省和噪声降低，并且可以无缝地取代后者，而不会中断设计流程和制造基础设施。更广泛的影响：研究结果有可能对计算、通信、雷达和其他高速电子应用产生重大影响。该项目将通过课程开发、研究成果传播和行业推广，开展一系列综合教育活动。将特别重视代表性不足的少数民族学生的教育和向高中或更低年级学生的推广。

The objective of this research is to develop a new clocking system for future-generation high-speed systems-on-chip such as high-performance multi-core microprocessors, in order to overcome the fundamental challenges in timing, noise and power consumption facing conventional clocking. In the proposed clocking scheme, a global clock is distributed across the chip, and then regenerated locally by injection-locked oscillators. The approach is based on a nonlinear circuit technique, injection locking, and a full suite of supporting technologies in systems, devices, and physics. Intellectual Merit: This project will advance the understanding of timing uncertainties in integrated systems, investigate potential challenges in injection-locked clocking, and develop multi-level (device, circuit, and system) techniques to address both. The proposed clocking scheme can deliver significant power savings and noise reduction compared to conventional clocking, and seamlessly replace the latter without disruption to the design flow and manufacturing infrastructures. Broader Impacts: The research results have the potential to critically impact computing, communications, radars, and other high-speed electronics applications. This project will enable a series of integrated educational activities through curriculum development, research results dissemination, and industry outreach. Special emphasis will be placed on under-represented minority student education and outreach to high school or younger students.