3D-Integrated Intra-Chip Free-Space Optical Interconnect for Future Multi-Core SoCs

适用于未来多核 SoC 的 3D 集成片内自由空间光学互连

• 批准号: 0829915
• 负责人: Hui Wu
• 金额: $ 90万
• 依托单位: University of Rochester
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-01 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0829915&HistoricalAwards=false
• 关键词: 3D; Integrated; Intra; Chip; Free

Moore?s Law continues to drive higher levels of system integration. Shrinking transistor size and increasing circuit complexity make it very difficult to transmit signals fast and reliably. In other words, the performance of these systems has become increasingly limited by communications between their building blocks. Future high performance multi-core microprocessors demand a fundamental change in intra- and inter-chip interconnect technologies. Optical interconnect is widely accepted as the long-term solution and significant progress has been made in recent years. However, on-chip optical interconnect, which is the focus of previous research efforts, presents some significant challenges. Pure-optical switching and storage devices in silicon technologies remain far from practical, and hence an optical interconnect network requires significant overhead of repeated optical-to-electrical and then electrical-to-optical conversions. Simultaneously, efficient silicon electro-optic modulators remain challenging due to either large size or small bandwidth, not to mention that both approaches require significant and expensive changes in standard silicon technologies. Both limitations will result in unacceptable delay, circuit complexity, cost, and energy consumption.This project will use free-space optics and supporting device, circuit, packaging, and architecture level techniques to create a CMOS-compatible, high-performance intra-chip interconnect technology. Integrated lasers, optical phase shifters. photodetectors and focusing microlens, will be implemented in GaAs or SiGe technologies, and 3-D integrated with CMOS circuits underneath, which will also include the transmitter and receiver electronics. This architecture allows point-to-point direct communication between any two nodes, bypassing the need for routing through intermediate nodes while managing packet collisions. This project will lead to a general technology and design framework applicable to a large variety of new applications in future high performance computing and other systems-on-chip.

摩尔？S律师继续推动更高水平的系统集成。晶体管尺寸的缩小和电路复杂性的增加使得快速可靠地传输信号变得非常困难。换句话说，这些系统的性能越来越受到其构建块之间的通信的限制。未来的高性能多核微处理器需要从根本上改变芯片内和芯片间的互连技术。光互连作为一种长远的解决方案被广泛接受，并在近年来取得了重大进展。然而，片上光互连是以往研究的重点，也带来了一些重大的挑战。硅技术中的纯光开关和存储设备仍远远不实用，因此光互连网络需要重复进行光电转换和电光转换的大量开销。同时，由于尺寸大或带宽小，高效的硅电光调制器仍然具有挑战性，更不用说这两种方法都需要对标准硅技术进行重大且昂贵的改变。这两个限制都将导致不可接受的延迟、电路复杂性、成本和能耗。该项目将使用自由空间光学技术和支持器件、电路、封装和体系结构级别的技术来创建一种与CMOS兼容的高性能芯片内互连技术。集成激光器，光学移相器。光电探测器和聚焦微透镜，将在GaAs或SiGe技术中实现，并在下面与CMOS电路进行3-D集成，这也将包括发射器和接收器电子设备。此架构允许任意两个节点之间的点对点直接通信，在管理数据包冲突时不需要通过中间节点进行路由。该项目将形成一个通用的技术和设计框架，适用于未来高性能计算和其他片上系统的各种新应用。