Architectures for Highly-Efficient 1000+ Core Chips for Compute and Data-Intensive Applications

“这项奖励是根据2009年美国复苏和再投资法案（公法111-5）资助的。”许多新兴和未来的电子应用需要大量的数字信号处理，并且在非常有限的功率预算下运行。例如：许多类型的无线通信、医学成像（如超声波）、传感器网络和便携式多媒体设备。处理这些工作负载的一个非常有前途的解决方案是包含一千个或更多的简单高效可编程处理器的单芯片平台。该项目的目标是：开发架构硬件概念和软件工具，以实现高性能和节能的计算平台，将结果引入加州大学戴维斯分校的几门课程，并使结果和工具广泛而容易地供其他研究人员使用。特别是，该项目的目标将通过探索：1)新的处理器间连接拓扑和处理器形状，2)将大型软件任务集合映射到处理器阵列的新算法，3)用于通用任务的专用硬件处理器，以及4)高效共享和可配置内存的体系结构来实现。pi活跃在几个校园范围内和全国性的组织中，这些组织致力于吸引和留住代表性不足的群体成员从事研究并完成科学和工程研究生学位。研究工作和结果将有助于未来科学家和工程师在设计大规模处理阵列方面的跨学科培训。

"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."Many emerging and future electronics applications require large amounts of digital signal processing, and operate with very limited power budgets. Examples include: many types of wireless communications, medical imaging such as ultrasound, sensor networks, and portable multimedia devices. A very promising solution for the processing of these workloads is a single-chip platform containing one thousand or more simple and highly-efficient programmable processors. The goals of this project are to: develop architectural hardware concepts and software tools that enable high-performance and energy-efficient computational platforms, introduce results into several courses at UC Davis, and make results and tools widely and easily available to other researchers. In particular, the project goals will be achieved by exploring: 1) novel inter-processor connection topologies and processor shapes, 2) new algorithms for mapping large collections of software tasks onto processor arrays, 3) specialized hardware processors for common tasks, and 4) architectures for efficient shared and configurable memories. The PIs are active in several campus-wide and national organizations that work to attract and retain members of under-represented groups to engage in research and complete graduate degrees in science and engineering. Research effort and results will be instrumental in the cross-disciplinary training of future scientists and engineers in the design of massive processing arrays.