SHF:Small:Fine-Grain Many-Core Processor Arrays for Efficient Enterprise Computing

SHF：小型：用于高效企业计算的细粒度众核处理器阵列

• 批准号: 1321163
• 负责人: Bevan Baas
• 金额: $ 40万
• 依托单位: University of California-Davis
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-10-01 至 2019-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1321163&HistoricalAwards=false
• 关键词: SHF; Small; Fine; Grain; Many

Data centers worldwide use approximately 30 billion watts of electricitywith data centers in the United States using approximately 8 to 10billion watts. Power consumption of datacenter systems is expected tocontinue to grow both absolutely and as a percentage of nationalconsumption. The goal of the proposed research is to develop massivelyparallel processor arrays that work in conjunction with traditionalenterprise-class processors to compute datacenter workloads with vastlygreater efficiency. The proposed research may lead to new applicationsand capabilities that were previously constrained by power dissipationor processing throughput.Project participants will propose, model, develop, and characterizenovel fine-grain many-core architectures, VLSI chip designs, andapplication algorithms for a processor array serving as a co-processoror functional unit. The proposed programmable fine-grained many-coreprocessor array contains no algorithm-specific hardware and is of a coregranularity that is very lightly explored in prior work. The array willoperate inside or near, and in co-ordination with a hostenterprise-class processor and compute key computational kernels oftenwith similar or higher performance than the host processor, but withorders of magnitude higher energy efficiency. During kernel computation,the host processor could attend to other tasks or enter a low powerstate. The targeted workloads include sorting, regular expression basedpattern matching, encryption, data compression, video encoding anddecoding, and other enterprise workloads of high impact that arediscovered during the course of the research.

全球数据中心使用约300亿瓦的电力，美国的数据中心使用约80亿至100亿瓦。数据中心系统的电力消耗预计将继续增长，无论是绝对的还是占全国消费的百分比。拟议研究的目标是开发与传统企业级处理器协同工作的并行处理器阵列，以极大地提高效率来计算数据中心工作负载。这项研究可能会带来新的应用和能力，以前受到功耗或处理吞吐量的限制。项目参与者将提出，建模，开发和表征新颖的细粒度众核架构，超大规模集成电路芯片设计，以及作为协处理器或功能单元的处理器阵列的应用算法。所提出的可编程细粒度多核处理器阵列不包含特定算法的硬件，是一个coregranularity，是非常轻的探索在以前的工作。该阵列将在内部或附近运行，并与主机企业级处理器协调，并计算关键计算内核，通常具有与主机处理器相似或更高的性能，但具有数量级更高的能效。在内核计算期间，主处理器可以处理其他任务或进入低功耗状态。目标工作负载包括排序、基于正则表达式的模式匹配、加密、数据压缩、视频编码和解码以及在研究过程中发现的其他具有高影响力的企业工作负载。