SHF: Medium: Collaborative Research: Throughput-Driven Multi-Core Architecture and a Compilation System

诸如多核处理器或现场可编程门阵列（FPGA）的计算基板共享具有通过路由结构互连的处理元件的二维阵列的特性。一方面，FPGA具有单输出可编程逻辑功能，另一方面，多核芯片具有复杂的32/64位处理核心。对于不同的应用，不同的可编程衬底产生最佳的面积-功率-性能权衡。这个项目正在开发一个大规模的多核基板，它有数百或数千个简单的处理核心沿着编译系统，将计算映射到这个结构上。这种多核架构名为Diastolic Array，比FPGA粒度更粗，但比传统的多核粒度更细。为了有效地利用这样大量的处理核，架构需要在空间上将计算映射到处理核并且将通信映射到点对点互连网络。为了实际可行，该映射过程必须自动化且有效。该项目通过同时开发硬件架构和编译系统来解决这一挑战。舒张期阵列芯片有望在一类有趣的应用中优于FPGA或通用处理器，从而实现更高效的原型设计和小批量生产。该项目的成果，如静态控制fi具有用于路由和资源分配的关联算法的互连架构也将适用于其他多核设计。最后，该项目正在开发一个新的并行处理模块，为本科计算机体系结构类，让初学者早期接触并行硬件，编写并行程序的经验，并使用编译器，利用并行。

Computing substrates such as multi-core processors or Field Programmable Gate Arrays (FPGAs) share the characteristic of having two-dimensional arrays of processing elements interconnected by a routing fabric. At one end of the spectrum, FPGAs have single-output programmable logic functions, and at the other end, multi-core chips have complex 32/64-bit processing cores. For different applications, different programmable substrates produce the best area-power-performance tradeoffs. This project is developing a large-scale multi-core substrate that has hundreds or thousands of simple processing cores along with a compilation system that maps computations onto this fabric. This many-core architecture, named Diastolic Array, is coarser-grained than FPGAs but finer-grained than conventional multi-cores. To efficiently exploit such a large number of processing cores, the architecture needs spatially mapping a computation to processing cores and communication to the point-to-point interconnect network. To be practically viable, this mapping process must be automated and effective. The project addresses this challenge by simultaneously developing hardware architecture and a compilation system. A diastolic array chip is expected to outperform FPGAs or general-purpose processors on an interesting class of applications, enabling more efficient prototyping and low-volume production. The outcomes of this project such as statically-configured interconnection architecture with associated algorithms for routing and resource allocation will also be applicable to other multi-core designs. Finally, the project is developing a new parallel processing module for an undergraduate computer architecture class to give sophomores early exposure to parallel hardware, experience with writing parallel programs and using compilers that exploit parallelism.