CSR: Small: Enabling High-Concurrency and Scalability for Many-Core Processors

为多核处理器实现高并发性和可扩展性我们正在开发一种适用于多核处理器的新型操作系统(OS)。由于功率和其他原因，微处理器的设计现在涉及到越来越多的核心，预计未来每个芯片的核心数量将达到100个或1000个。即使对主流应用程序来说，向高并发性的转变也意味着需要简化并发编程，以及需要能够管理和提供高并发性的操作系统。第一步是利用操作系统和编译器可以在不需要并发控制的情况下使用的“私有”内存，从而实现简单性和高性能。有了操作系统和编译器的支持，这种最简单的并发管理形式可以更频繁地使用，我们可以检测到隐私假设无效的时间，从而防止一类错误。对于较复杂的并发模式，我们将编译器分析与动态锁定相结合，使我们能够根据争用量自适应地从各种同步方法中进行选择，并通过静态和动态分析相结合来检查常见的同步错误。最后，内置的推测执行使得能够隐藏长时间运行的任务的延迟，例如异步I/O操作。有了许多内核，我们现在可以推测地并行执行几条路径。此外，这些机制可用作用于容错的轻量级检查点/重启，特别是针对暂时性或非确定性错误，从而简化高可用性应用程序。

Enabling High-Concurrency and Scalability for Many-Core ProcessorsWe are developing a novel operating system (OS) for many-core processors. For power and other reasons, microprocessor designs now involve increasing numbers of cores, with an expectation of 100s or 1000s of cores per chip in the future. The movement to high concurrency even for mainstream applications implies the need to simplify concurrent programming and the need for an OS capable of managing and delivering high concurrency.The first step is to leverage "private" memory, which the OS and the compiler can use without the need for concurrency control, thus achieving both simplicity and high performance. With OS and compiler support, this simplest form of concurrency management can be used more often and we can detect when the privacy assumption is not valid, thus preventing one class of errors. For "embarrassingly" parallel applications, this model often suffices.For more complex concurrency patterns, we combine compiler analysis with dynamic locking, which allows us to choose adaptively from a variety of synchronization methods based on the amount of contention, and also check for common synchronization errors through a combination of static and dynamic analysis.Finally, built-in speculative execution enables latency hiding for long-running tasks, such as asynchronous I/O operations. With a many cores we can now speculatively execute several paths in parallel. Additionally, these mechanisms can be used as a lightweight checkpoint/restart for fault tolerance, especially for transient or non-deterministic bugs, thus simplifying high-availability applications.