SHF: Medium: Compiling Parallel Algorithms to Memory Systems

这个项目旨在改进并行编程的实践——这可能是21世纪计算机科学面临的核心问题。虽然冯·诺伊曼和其他人首先引入的顺序模型很好地服务于我们，但它的低效率已经被十亿晶体管芯片的可用性引起了强烈的关注，这些芯片在运行顺序算法时大大未被充分利用，而且非常耗电。该项目旨在提高分布式存储系统的可编程性和效率，这是并行算法执行的关键问题。虽然在一个芯片上放置数千个独立的加法器相当容易，但为它们提供有用的数据要困难得多，这一任务落在了存储系统上。这项研究将开发编译器优化算法，能够配置和编排能够利用这种并行计算资源的并行存储系统。为了取得更大的进展，该项目在两个重要方面背离了现有的霸权。首先，它的技术将只应用于以函数风格表达的算法，这是一种更抽象、数学上合理的表示，可以对并行算法和非常积极的优化进行精确推理。其次，它的目标是现场可编程门阵列（fpga），而不是现有的并行计算平台。fpga提供了一个高度灵活的平台，可以探索与当今笨拙的解决方案截然不同的并行架构，这些解决方案主要是将遗留的顺序架构粘合在一起。虽然fpga过于灵活和耗电，无法成为并行计算机体系结构问题的长期“解决方案”，但它们的使用使该项目基于物理现实，并将产生有用的硬件合成算法作为副作用。明智而高效的数据移动是并行计算的关键。这个项目直面挑战，建立硬件和软件有效地一起操作数据所需的结构和算法。这项研究将为下一代存储和指令集体系结构、编译器和编程范例奠定基础——这是当今主流计算的基石。

This project aims to improve the practice of parallel programming - perhaps the central problem facing computer science in the 21st century. While the sequential model first introduced by Von Neumann and others has served us well, its inefficiency has been brought into sharp focus by the availability of billion-transistor chips, which are greatly underutilized yet power-hungry when running sequential algorithms.This project aims to improve the programmability and efficiency of distributed memory systems, a key issue in the execution of parallel algorithms. While it is fairly easy to put, say, thousands of independent adders on a single chip, it is far more difficult to supply them with useful data to add, a task that falls to the memory system. This research will develop compiler optimization algorithms able to configure and orchestrate parallel memory systems able to utilize such parallel computational resources.To make more than incremental progress, this project departs from existing hegemony in two important ways. First, its techniques will be applied only to algorithms expressed in the functional style, a more abstract, mathematically sound representation that enables precise reasoning about parallel algorithms and very aggressive optimizations. Second, it targets field-programmable gate arrays (FPGAs) rather than existing parallel computing platforms. FPGAs provide a highly flexible platform that enables exploring parallel architectures far different than today's awkward solutions, which are largely legacy sequential architectures glued together. While FPGAs are far too flexible and power-hungry to be the long-term "solution"to the parallel computer architecture question, their use grounds this project in physical reality and will produce useful hardware synthesis algorithms as a side-effect.Judicious and efficient data movement is the linchpin of parallel computing. This project attacks that challenge head on, establishing the constructs and algorithms necessary for hardware and software to efficiently manipulate data together. This research will lay the groundwork for the next generation of storage and instruction set architectures, compilers, and programming paradigms -- the bedrock of today's mainstream computing.