CAREER: Predicting Timing Violations: A New Direction for Robust System Design

时序冲突是快速技术扩展的产物，体现了微处理器设计中的一个核心可靠性挑战。计时违规领域的大量现有技术可分为两大类：被动性和主动性。在这两种方案中，缺乏足够的时间来识别即将到来的时序违规分别限制了纠正技术的范围，导致大量的恢复开销或故障覆盖的损失。使用结合了应用、架构和电路层信息的跨层分析，这个职业项目展示了可以提前几个时钟周期预测时序违规。对时序违规的早期预测可以在健壮的系统设计中提供巨大的杠杆作用，为未来的系统研究开辟一个有前途的方向。在这种模式下，微处理器可以在更紧密的频率下运行，在这种频率下，可预测的错误经常发生，并且可以容忍最小的性能损失。这种系统设计风格可以重塑物理设计算法，提升微处理器组件的能效前沿。对跨层设计这一新兴领域的研究将使电路设计师和系统架构师能够增加协作设计，并开发负担得起、节能和可靠的计算机系统。集成电路的快速增长和发展为应对即将到来的挑战创造了对计算机工程技能的巨大需求。该职业项目寻求培养一批未来的工程师，能够通过有针对性的知识传播来解决集成电路中日益增长的不可靠性问题。将通过犹他州立大学现有的平台，如女工程师协会(SWE)、工程州立大学和妇女与性别中心(CWG)项目，积极寻求本科生、女性和少数族裔的参与。

Timing violations, an artifact of rapid technology scaling, embody a central reliability challenge in microprocessor design. A vast body of existing techniques in the landscape of timing violations fall under two broad categories: reactive and proactive. In both of these schemes, the lack of sufficient time in identifying an upcoming timing violation limits the scope of corrective techniques, incurring a large recovery overhead, or loss in fault coverage, respectively. Using a cross-layer analysis combining information from the application, architecture and circuit layers, this CAREER project demonstrates that timing violations can be predicted several clock cycles early. Early prediction of timing violations can offer a vast leverage in robust system design, opening up a promising direction for future systems research. In this paradigm, microprocessors can operate at a tighter frequency, where predictable errors frequently occur and are tolerated with minimal performance loss. Such a system design style can reshape physical design algorithms, boosting the energy efficient frontiers for microprocessor components. Research in the nascent area of cross-layer design will enable circuit designers and system architects to increase collaborative design, and develop affordable, energy efficient and reliable computer systems. The rapid growth and evolution of integrated circuits creates a huge demand of Computer Engineering skill sets for addressing upcoming challenges. The CAREER project seeks to create a stream of future engineers capable of tackling growing unreliability in integrated circuits through focused knowledge dissemination. Undergraduates, women and minorities will be actively sought for participation through the existing platforms at Utah State University such as the Society of Women Engineers (SWE), Engineering State and Center for Women and Gender (CWG) programs.