CSR: Small: DARP: Promoting Energy Efficient System Design Through a Dynamically Adaptable Resilient Pipeline

包括延迟的晶体管行为的可变性传统上通过以能量效率为代价的电路级的过度保守的设计选择来减轻。 本项目的目标是通过对可变延迟管道的研究，开发在建筑层面更有效地管理延迟的技术。 该项目的长期目标是提高计算机的能源效率。该项目涉及在核心级别和系统级别管理应用程序引起的管道延迟变化，概述了促进可持续计算的变革性方法。该项目提倡跨层电路架构设计主题，这对于未来的系统设计来说是必不可少的。这个项目的各种研究任务探讨了流水线微处理器中电路级延迟的可变性，展示了三个有趣的轴：（a）时间-在程序的不同阶段，在给定的管道阶段内的延迟变化;（B）空间-微处理器的不同管道阶段之间的不同延迟分布;和（c）工作负载-在各种工作负载中看到的各种管道阶段的独特延迟曲线。这些被仔细分析，以设计一个动态适应弹性管道（DARP），它概述了下一波的创新，推动能源效率的前沿流水线微处理器设计。通过跨层基础设施的教育活动，该项目将有助于创造一个未来的工作队伍，在可持续的计算机设计中练习跨层主题。

Variability of transistor behavior including delay has traditionally been mitigated through overly conservative design choices at the circuit level that come at the expense of energy efficiency. The objective of this project is to develop techniques for more effectively managing delay at the architectural level through the study of variable-delay pipelines. The long-term goal of the project is to improve the energy efficiency of computers.This project involves managing application induced pipeline delay variability, both at the core level and at the system level, outlining a transformative approach to promote sustainable computing. The project advocates cross-layer circuit-architectural design themes, which are becoming indispensable for future system designs. Various research tasks of this project explore circuit level delay variability in a pipelined microprocessor by demonstrating three intriguing axes: (a) temporal--delay variation within a given pipe stage during different phases of a program; (b) spatial--distinct delay distributions among different pipe stages of a microprocessor; and (c) workload--unique delay profiles of various pipe stages seen among various workloads. These are carefully analyzed to design a Dynamically Adaptable Resilient Pipeline (DARP), which outlines a next wave of innovation in pushing the energy efficient frontier of pipelined microprocessor design. Through educational activities with the cross-layer infrastructure, this project will be instrumental in creating a future work force well placed to exercise cross-layer themes in sustainable computer design.