CAREER: An Integrated Treatment of Voltage Noise and Process Variability in Many-core and GPU Systems with Microarchitectural Solutions

几十年来，微处理器技术的进步一直是计算机行业增长的主要引擎。由于技术和微体系结构的创新，微处理器的性能多年来以惊人的速度提高。不幸的是，近年来技术扩展陷入了僵局。低纳米尺寸芯片制造工艺的重大挑战导致晶体管行为的高度可变性，从而导致性能降低、功耗增加和对错误的敏感性增加。一般来说，高可变性导致更大的设计裕度，使芯片的能效降低。这些技术挑战发生在对节能计算需求最大的时候。随着基于云计算的迅速普及和智能移动的设备的爆炸式增长，能源效率现在对从服务器到智能手机的整个计算市场范围至关重要。要在这些系统中实现持续的性能增长，需要大幅提高计算的能源效率。在这项工作中，正在开发新的微架构和软件解决方案，以降低未来芯片的设计裕度，在确保可靠运行的同时实现大幅节能。这些解决方案在计算环境的多个层面上采用变化感知设计，包括微架构创新、新固件和基于操作系统的调度和电源管理解决方案。为此目的，正在开发首次整合多种可变性来源的新技术模型，从而能够设计具有可变性的解决方案。这项工作确定了影响具有大量计算单元（如众核和图形处理器）的芯片中电源电压稳定性的新的可靠性挑战。它开发了新颖的工艺和电压变化感知调度和电源管理算法，可降低电压不稳定性，消除对大而低效的设计裕度的需求。在微架构和固件级别的工作开发了新的机制，通过利用片上弹性机制，以确保可靠和高效的执行动态降低电压裕度。这些解决方案极大地提高了计算的能源效率，因此预计将对计算行业和整个社会产生重大影响。

Advances in microprocessor technology have been the main engines for growth in the computing industry for decades. Microprocessor performance has improved at a remarkable rate for many years owing to technological and microarchitectural innovations. Unfortunately technology scaling has reached an impasse in recent years. Significant challenges with the chip manufacturing process in low-nanometer dimensions are causing high variability in transistor behavior leading to lower performance, higher power consumption and higher susceptibility to errors. In general, high variability leads to larger design margins making chips less energy efficient. These technological challenges are happening at a time when the need for energy efficient computing is greatest. With the rapid proliferation of cloud-based computing and the explosion of smart mobile devices energy efficiency is now crucial to the entire range of computing markets from servers to smartphones. Achieving continued performance growth in these systems going forward requires dramatic improvements in the energy efficiency of computation.In this work, new microarchitectural and software solutions for lowering design margins in future chips are being developed, achieving substantial energy reduction while ensuring reliable operation. These solutions employ variation-aware design across multiple layers of the computing environment including microarchitectural innovations, new firmware and operating system-based scheduling and power management solutions. New technology models that for the first time integrate multiple sources of variability are being developed for this purpose, enabling the design of variation-aware solutions. The work identifies new reliability challenges that affect supply voltage stability in chips with large numbers of compute units such as many-core and graphics processors. It develops novel process and voltage variation-aware scheduling and power management algorithms that reduce voltage instability eliminating the need for large and inefficient design margins. At the microarchitectural and firmware levels the work develops new mechanisms for dynamically reducing voltage margins by leveraging on-chip resiliency mechanisms to ensure reliable and efficient execution. These solutions are dramatically improving the energy efficiency of computation and are therefore expected to have a significant impact on the computing industry and society in general.