A Hardware-Accelerated Transistor-to-Application SEU Simulation Platform

随着晶体管尺寸的缩小，它们可以在相同面积的硅上实现更多功能。然而，由于阿尔法粒子撞击硅，小型晶体管也更容易出现间歇性错误。让工程系统容忍此类错误是一个问题，随着时间的推移，这个问题将变得越来越重要。传统上，评估容错设计几乎是不可能的，因为(I)故障很少发生，(Ii)它们需要非常详细(因此耗时)的模拟来确定它们是否具有任何实际效果，以及(Iii)需要执行数百万甚至数十亿这样的模拟来确定设计是否确实能够容忍具有不同特征的粒子撞击。这个项目通过一组联锁模拟器来解决这个问题，每个模拟器的精度和模拟速度都不同。最初的粒子撞击在很短的时间内以极高的细节进行建模，直到可以使用更快的模拟器以较少的细节进行建模，依此类推。如何智能地决定粒子何时撞击、撞击什么以及何时在模拟器之间过渡是该项目的一些核心智能组件。这样的模拟器可以帮助开发技术，建立比今天更有效和更可靠的系统。

As transistors shrink in size, they enable more functionality on the same area of silicon. However, small transistors are also more susceptible to intermittent errors due to alpha particles striking the silicon. Engineering systems to tolerate such errors is a problem that will become increasingly important over time. Evaluating fault tolerant designs has traditionally been almost impossible because (i) faults occur very infrequently, (ii) they require highly detailed (and thus time-consuming) simulations to determine whether they have any real effect, and (iii) millions or even billions of such simulations need to be performed to determine whether the design can actually tolerate particle strikes with different charateristics. This project addresses the problem through a set of interlocking simulators, each at a different level of accuracy and simulation speed. The initial particle strike is modeled in extremely high detail for a short time until it can be modeled by a faster simulator with less detail, and so on. How to intelligently decide when the particle strikes, what it strikes, and when to transition between simulators are some of the core intellectual components of this project. Such a simulator could help develop techniques to build more efficient and effective reliable systems than are possible today.