CAREER: Tools for Design for Manufacturability in Nanometer CMOS
职业:纳米 CMOS 可制造性设计工具
基本信息
- 批准号:0347403
- 负责人:
- 金额:$ 40万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Continuing Grant
- 财政年份:2004
- 资助国家:美国
- 起止时间:2004-08-15 至 2010-07-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
PROPOSAL NO: 0347403INSTITUTION: U of Texas AustinPRINCIPAL INVESTIGATOR: Orshansky, MichaelTITLE: Tools for Design for Manufacturability in Nanometer CMOSThe goal of this research is to develop models, algorithms, and conceptual frameworks that will enable robust circuit design in nanometer scale CMOS technology. The manufacturing and fundamental limitations of scaled solid-state technology lead to increasing unpredictability in the physical properties of semiconductor devices. This research proposes a new design paradigm in which uncertainty is explicitly embraced by computer-aided design tools. This will be achieved via the unified treatment of statistical modeling, analysis, and optimization. This proposal specifically aims at: (1) Developing an analysis environment for early assessment of the impact of process and device variation on circuit design. The tool will assist in making high-level decisions on the properties of new designs and technologies. (2) Developing an accurate and efficient statistical static timing analysis algorithm which will allow circuit designers to reliably verify the timing behavior of their designs and find the distribution of circuit timing yield. (3) Developing statistical circuit optimization approaches that will enable identifying superior design alternatives with respect to frequency, power, and yield. The goal of the educational part of this program is to ensure that a new generation of engineering students has a comprehensive understanding of both the semiconductor physics and technology and the algorithmic circuit design techniques. To achieve that goal, this proposal will: (1) develop two new courses emphasizing joint treatment of concepts in solid-state technology, circuit design, and computer-aided design algorithms; (2) actively recruit underrepresented students through direct outreach and targeted research opportunities for undergraduates; and (3) promote active involvement of industrial experts in teaching.
提案编号:0347403机构:得克萨斯州奥斯汀大学校长:Orshansky,迈克尔标题:纳米CMOS可制造性设计工具本研究的目标是开发模型,算法和概念框架,使纳米级CMOS技术的强大电路设计。规模化固态技术的制造和基本限制导致半导体器件的物理特性的不可预测性增加。本研究提出了一种新的设计范式,其中不确定性是明确接受计算机辅助设计工具。这将通过统计建模、分析和优化的统一处理来实现。本建议的具体目标是:(1)开发一个分析环境,用于早期评估工艺和器件变化对电路设计的影响。该工具将有助于就新设计和技术的特性做出高级别决策。(2)开发一种准确有效的统计静态时序分析算法,使电路设计人员能够可靠地验证其设计的时序行为,并找到电路时序成品率的分布。(3)开发统计电路优化方法,以确定频率、功率和成品率方面的上级设计方案。该计划的教育部分的目标是确保新一代工程专业的学生全面了解半导体物理和技术以及算法电路设计技术。为了实现这一目标,该提案将:(1)开发两门新课程,强调固态技术、电路设计和计算机辅助设计算法中概念的联合处理;(2)通过直接推广和针对本科生的有针对性的研究机会,积极招募代表性不足的学生;(3)促进工业专家积极参与教学。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Michael Orshansky其他文献
Michael Orshansky的其他文献
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{{ truncateString('Michael Orshansky', 18)}}的其他基金
SHF: Medium: Simulation-Based Analysis of EM Side Channels in Embedded Systems: From Software to Fields
SHF:媒介:嵌入式系统中电磁侧通道的基于仿真的分析:从软件到现场
- 批准号:
1901446 - 财政年份:2019
- 资助金额:
$ 40万 - 项目类别:
Continuing Grant
STARSS: Small: Simulation-Based Verification of EM Side-Channel Attack Resilience of Embedded Cryptographic Systems
STARSS:小型:基于仿真的嵌入式加密系统的 EM 侧信道攻击弹性验证
- 批准号:
1527888 - 财政年份:2015
- 资助金额:
$ 40万 - 项目类别:
Standard Grant
SaTC: STARSS: Hardware Authentication through High-Capacity PUF-Based Secret Key Generation and Lattice Coding
SaTC:STARSS:通过基于大容量 PUF 的密钥生成和点阵编码进行硬件身份验证
- 批准号:
1441484 - 财政年份:2014
- 资助金额:
$ 40万 - 项目类别:
Standard Grant
A Hardware-Accelerated Transistor-to-Application SEU Simulation Platform
硬件加速晶体管到应用 SEU 仿真平台
- 批准号:
1255757 - 财政年份:2013
- 资助金额:
$ 40万 - 项目类别:
Continuing Grant
SHF: Small: Overcoming Nanoscale Modeling Challenges in Analog Synthesis: A Data-Driven Paradigm for Optimization of Approximate Functions
SHF:小:克服模拟合成中的纳米级建模挑战:用于优化近似函数的数据驱动范例
- 批准号:
1116955 - 财政年份:2011
- 资助金额:
$ 40万 - 项目类别:
Standard Grant
Formal Techniques for Adaptive Circuit Fabrics
自适应电路结构的形式技术
- 批准号:
0541330 - 财政年份:2006
- 资助金额:
$ 40万 - 项目类别:
Continuing Grant
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