SBIR Phase II: Analog/Mixed-Signal Integrated Circuit Verification Coverage

该项目的更广泛的影响/商业潜力是通过提高A/MS设计验证的质量、提高首次通过设计的成功率和缩短上市时间来增加美国半导体行业的竞争力。今天，当前的模拟验证方法和工具经常无法发现设计错误，特别是由于芯片子系统之间的不可预见的相互作用，并且这些错误经常导致产品上市的代价高昂的延迟，即使在模拟只占整体设计的一小部分的芯片上？630亿美元的市场。与多个设计版本相关的成本和潜在利润损失可能很快就会达到数百万美元，很容易让设计师获得适当设计工具的成本相形见绌。使用两种不同的市场分析，第一种使用数字验证市场类比，第二种仅在AMS IC市场考虑全球新的(不是轻微的衍生)设计，导致估计新的模拟验证解决方案的总可用市场年收入为3亿美元。通过分析和协作工具进一步扩展验证解决方案可能会使市场进一步增长50%，达到4.5亿美元的年收入。了解A/MS验证覆盖范围是此机会的关键组成部分。该小型企业创新研究(SBIR)第二阶段项目提出了模拟/混合信号(A/MS)集成电路开发的验证覆盖系统。今天的验证？S复杂的集成电路和系统被广泛认为是提高设计生产率的关键挑战。核查挑战的一部分涉及了解作业空间的哪一部分已被检查；即？被覆盖？目前已有公认的形式技术和基于模拟的技术来捕获和测量数字集成电路的测试覆盖率，但没有相应的商业能力用于模拟和混合信号集成电路。模拟设计人员经常花费太多时间来分析和过度测试一小部分已被充分理解的使用场景的系统行为，而将状态空间的很大一部分完全留在未经测试的状态。由于与这些类型的电路相关的固有的大的设计空间，A/MS电路的设计探索问题对实现这样的系统提出了一个关键的挑战。该项目的主要目标包括生产和扩展在第一阶段原型中演示的关键组件。该项目将提供一种商业产品，以提供可操作的A/MS核查覆盖面数据，并促进设计和核查小组之间的合作。由此产生的产品将具有处理大型复杂设计的可扩展性和性能。

The broader impact/commercial potential of this project is to increase the competitiveness of U.S. semiconductor industry by improving the quality of A/MS design verification, improving first pass design success and reducing time-to-market. Today, current analog verification methods and tools often fail to catch design mistakes, especially due to unforeseen interactions across chip subsystems, and these mistakes are a frequent cause of costly delays in bringing products to market even on chips where analog is only a small portion of the overall design ? a $63 billion market. The costs and lost profit potential related to multiple design versions can quickly run to millions of dollars and easily dwarfs the cost of providing designers access to the appropriate design tools. Using two different market analyses, the first using a digital verification market analogy and the second considering worldwide new (not slight derivatives) designs in just the AMS IC market, leads to an estimation of total available market for new analog verification solutions of $300 million annual revenue. Further extending the verification solutions with analytics and collaboration tools can potentially increase the market by a further 50% to $450 million annual revenue. Understanding A/MS verification coverage is a key component of this opportunity.This Small Business Innovation Research (SBIR) Phase 2 project proposes a verification coverage system for analog/mixed-signal (A/MS) integrated circuit development. Verification of today?s complex integrated circuits and systems is widely acknowledged as a critical challenge to improving design productivity. Part of the verification challenge revolves around understanding what portion of the operating space has been examined; i.e., ?covered?. Today well-accepted formal and simulation-based techniques exist to capture and measure test coverage for digital integrated circuits, but there is no corresponding commercial capability for analog and mixed-signal integrated circuits. Analog designers frequently spend too much time analyzing and over-testing system behavior for a small set of well understood usage scenarios while leaving significant portions of the state-space completely untested. The design exploration problem for A/MS circuits presents a critical challenge for implementing such systems due to the inherently large design space associated with these types of circuits. Key objectives for the project include productizing and extending key components demonstrated in the Phase 1 prototype. This project will deliver a commercial product to provide A/MS verification coverage data that is actionable and facilitates collaboration between design and verification teams. The resulting product will have scalability and performance to handle large complex designs.